CoreRxIODBitAlign IP available from the Libero SoC Catalog performs training when interfacing the IOD macro to support as a dynamic source with adjusting delays to capture the data correctly.

Figure 1. CoreRxIODBitAlign Implementation Diagram
Note: HS_IO_CLK is internal connection.

This CoreRxIODBitAlign IP works based on Fabric clock (OUT_FABCLK*) from CCC or PLL component and PF_IOD_GENERIC_RX IOD component works based on OUT*_HS_IO_CLK_* or for bit alignment.

An example application for Bit Alignment uses the PF_IOD_GENERIC_RX IOD component to receive the serial data with a required data rate of 1000 Mbps in DDRx4 fabric mode. The OUT2_FABCLK_0 or SCLK should be driven from the PLL or CCC component at 125 MHz and OUT0_HS_IO_CLK_0 to PF_IOD_GENERIC_RX at 500 MHz.

The CoreRxIODBitAlign IP starts the training when the PLL_LOCK is stable and driven high. The LP_IN input is used only in the CoreRxIODBitAlign IP when MIPI_TRNG parameter is set to 1. This LP_IN signaling is active low and level-based, detected as neg edge every time by the IP to indicate the valid start of frame to start the bit alignment training mechanism. If MIPI_TRNG parameter is set to 0, then this input is left unused by the IP.

The CoreRxIODBitAlign IP indicates the start of training by driving BIT_ALGN_START high and BIT_ALGN_DONE as low. It then drives the output BIT_ALGN_LOAD to load the default settings in the PF_IOD_GENERIC_RX component. The BIT_ALGN_CLR_FLGS is used to clear the IOD_EARLY, IOD_LATE and BIT_ALGN_OOR flags.

The CoreRxIODBitAlign IP proceeds with BIT_ALGN_MOVE followed with BIT_ALGN_CLR_FLGS for every TAP and records the IOD_EARLY, IOD_LATE flags. When BIT_ALGN_OOR is set high by the PF_IOD_GENERIC_RX component, then the CoreRxIODBitAlign IP sweeps the recorded EARLY and LATE flags and finds the optimal EARLY and LATE flags to calculate the required TAP delays for clock and data bit alignment.

The CoreRxIODBitAlign IP loads the calculated TAP delays and drives BIT_ALGN_START low and BIT_ALGN_DONE high to indicate the completion of the training.

The CoreRxIODBitAlign IP continues the Re-training dynamically if it detects noisy IOD_EARLY or IOD_LATE feedback assertion from PF_IOD_GENERIC_RX component. The BIT_ALGN_DONE is reset and driven low and BIT_ALGN_START is driven high again by the CoreRxIODBitAlign IP to indicate the restart of the training. The timeout counter when reaches the timeout condition asserts the BIT_ALGN_ERR at the end of the training.

The CoreRxIODBitAlign IP also provides restart mechanism for the user to restart the training whenever required. The BIT_ALGN_RSTRT input is active high level should be driven high (for example, 8 clocks). The BIT_ALGN_DONE is reset and driven low. BIT_ALGN_START is driven high again by the CoreRxIODBitAlign IP to indicate the fresh start of the training.

The CoreRxIODBitAlign IP also provides hold mechanism to hold the training in the middle. In this use case, the HOLD_TRNG parameter should be set to 1 then the CoreRxIODBitAlign IP uses the BIT_ALGN_HOLD input and asserts active high level-based until it requires the CoreRxIODBitAlign IP to hold the training and then continues the training when the input BIT_ALGN_HOLD is driven low.

Figure 2. CoreRxIODBitAlign Training State Diagram

For more information about IP module usage, see HB0861: CoreRxIODBitAlign Handbook. This handbook can be downloaded from the Libero SoC Catalog.

The following figure shows the CoreRxIODBitAlign Libero SoC Configurator.

Figure 3. CoreRxIODBitAlign Libero SoC Configurator