LVDS in GPIO Banks with VDDI = 1.8 V

LVDS inputs and outputs in the GPIO banks are supported from Libero SoC with VDDI = 1.8 V and VDDAUX= 2.5 V or 3.3 V. Both LVDS18G inputs and outputs operate from the VDDAUX power supply, which allows operation independent of the VDDI power supply. LVDS18G inputs include on-chip differential termination, and true high-speed differential outputs are used in LVDS18G. The LVDS18G IOSTD is supported only for input and output I/Os (TRIBUF and INOUT is not supported).

LVDS18G I/O standard allows Libero SoC to set VDDI = 1.8V, thereby place other 1.8 V I/O on the bank as mixed voltage support, and simultaneously support the LVDS modes ( see respective PolarFire FPGA Datasheet or PolarFire SoC Advance Datasheet). If setting the I/O standards from IOEditor or pdc with VDDI = 1.8 V, it requires the selection of LVDS18G as I/O TYPE and VDDAUX = 2.5 V (3.3 V) circuit board voltage supply. LVDS18G input requires Clamp Diode to be OFF when placed on a bank with VDDI = 1.8.