Output Register

The following illustration shows the output register.

Figure 1. Output Register

The following table lists the output register pins and their descriptions.

Table 1. I/O Output Register Ports
Ports Types Descriptions
CLK Input Clock input
D Input Data input
Q Output Data output
EN Input Clock enable (active high)
SL Input Synchronous load (active high)
LAT Input Latch enable (active high)
SD_B Input Synchronous data
AD_B Input Asynchronous data (active low)