Interface Ports

The following table lists the RX_DDR_B_C and RX_DDR_B_A interface mode ports.

Table 1. RX_DDR_B_C and RX_DDR_B_A Interface Mode Ports1
Port I/O Description
RX Input Input DDR data. Supports up to 128-bits for _G interfaces and 11-bit for _R interfaces.
RX_CLK Input Input DDR clock.
ARST_N Input Asynchronous reset to IOD and lane controller. ARST_N inputs are independent asynchronous resets to both the Rx and Tx IOD blocks.
HS_IO_CLK_PAUSE Input Toggling the HS_IO_PAUSE:

– Resets the IOD RX state machines. This reset re-synchronizes pattern to HS_IO_CLK (bank clock) and RXCLK.

– Resets any adjustment done through SLIP operation.

– Resets the IOD TX state machines. This reset synchronizes HS_IO_CLK and TXCLK.

– HS_IO_CLK_PAUSE must be pulsed after PLL lock is asserted in fractional aligned mode allowing the I/O Gearing state machine to detect the phase difference between fabric clock and clock coming out of PLL.

L#_RX_DATA[m:0] Output DDR output to FPGA fabric. ‘m’ equals the output pins from the geared DDR component to the fabric where the even numbered pin is the rising edge data and the odd numbered pin is the falling edge data of the DDR signal. The number of fabric pins are based on the number of I/Os and the gearing ratio.

L# is associated with the # of external input pins up to 128 maximum.

RX_CLK_G Output Receive clock to FPGA fabric using a global (G) or regional (R) clock. Global and regional can be used for aligned interfaces. Center-aligned interfaces can only use global clock.
(1) Other pins are visible when advanced options are used. See Generic IOD Interface Implementation.