The latency listed in the following table is an approximation and based on a specific fixed relationship for HSIO_CLKS clocks and regional clocks. Due to the flexibility and training associated with the DDR interfaces, the latency can be different than that listed by ┬▒1 cycle.

Table 1. Latency for the Rx/Tx CLK Interface
IOD Mode Direction Latency Cycle (Rx/Tx CLK)
RX_DDRX1 Input 1
RX_DDRX2 Input 4
RX_DDRX3P5 Input 6
RX_DDRX4 Input 7
RX_DDRX5 Input 9
TX_DDRX1 Output 2.5
TX_DDRX2 Output 5.5
TX_DDRX3P5 Output 6
TX_DDRX4 Output 10.5
TX_DDRX5 Output 13.5