Low-Voltage Differential Signal (LVDS)

LVDS (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. The voltage swing between two signal lines is approximately 350 mV. GPIO supports LVDS receive and transmit modes. HSIO supports LVDS receive mode with an external 100 Ω board termination, see I/O External Termination for more information.