HS_IO_CLK Generation Using PF_IOD_CDR_CCC

The PF_IOD_CDR receive interface is sourced by a single PLL driving four bank clocks of 0, 90, 180, and 270 degrees running at the data rate. PF_IOD_CDR_CCC is available in the Libero SoC IP catalog. The PF_IOD_CDR transmit interface uses fabric clock on OUT0 port of the PLL and generates the transmit clock.

The following illustration shows the PF_IOD_CDR interface connected to the IOD_CDR_CCC and fabric logic.

Figure 1. Using PF_IOD_CDR Interfaces