Clock Sharing

The same PLL is shared between the PF_IOD_CDR receive and transmit interfaces, as shown in Figure 1. In addition, multiple PF_IOD_CDR interfaces can share the same PLL on the adjacent vertical and horizontal edges. For instance, the PLL_SW_0 interface can drive the PF_IOD_CDR interface on the southern and western edges (see I/O Banks).

The following illustration shows multiple PF_IOD_CDR transmit and receive interfaces.

Figure 1. Multiple PF_IOD_CDR Transmit and Receive Interfaces