Flash

SAM L10/L11 devices embed 16 KB, 32 KB or 64 KB of internal Flash mapped at address 0x0000 0000.

The Flash has a 512-byte (64 lines of 8 bytes) direct-mapped cache which is enabled by default after power up.

The Flash is organized into rows, where each row contains four pages. The Flash has a row-erase and a page-write granularity.

CAUTION: For this Flash technology, a maximum number of 8 consecutive writes is allowed per row. Once this number is reached, a row erase is mandatory.

Table 1. Flash Memory Parameters
Device	Memory Size [KB]	Number of Rows	Row size [Bytes]	Number of Pages	Page size [Bytes]
SAM L11x16 / SAM L10x16 ⁽¹⁾	64	256	256	1024	64
SAM L11x15 / SAM L10x15 ⁽¹⁾	32	128	256	512	64
SAM L11x14 / SAM L10x14 ⁽¹⁾	16	64	256	256	64

Note:

1.x = E or D.

The Flash is divided in different regions. Each region has a dedicated lock bit preventing from writing and erasing pages on it. Refer to the NVM Memory Organization figures in the chapter “NVMCTRL” to get the different regions definition.

Note: The regions size is configured by the Boot ROM at device startup by reading the NVM Boot Configuration Row (BOCOR). Refer to the Boot ROM chapter for additional information.

Table 2. Flash Lock Regions Parameters
Device	SAM L10	SAM L11
Number of Flash Lock Regions	2	4
Regions Name	Flash (BOOT region) / Flash (APPLICATION region)	Secure Flash (BOOT region) / Non-Secure Flash (BOOT region) Secure Flash (APPLICATION region) / Non-Secure Flash (APPLICATION region)