NONSECC

Peripheral Non-Secure Status - Bridge C

This register is loaded from UROW at boot.

Important: This register is only available for SAM L11 and has no effect for SAM L10.

Reading NONSEC register returns peripheral Security Attribution status:

Value Description
0 Peripheral is secured.
1 Peripheral is non-secured.
  0x5C 32 Write-Secure x initially determined from NVM User Row after reset  
Parent topic: Register Description

Peripheral Non-Secure Status - Bridge C

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
      TRAM OPAMP CCL TRNG PTC DAC  
Access      R/R/R R/R/R R/R/R R/R/R R/R/R R/R/R  
Reset      x x x x x x  
Bit  7 6 5 4 3 2 1 0  
  ADC TC2 TC1 TC0 SERCOM2 SERCOM1 SERCOM0 EVSYS  
Access  R/R/R R/R/R R/R/R R/R/R R/R/R R/R/R R/R/R R/R/R  
Reset  x x x x x x x x  

Bit 13 – TRAM: Peripheral TRAM Non-Secure

Peripheral TRAM Non-Secure

Bit 12 – OPAMP: Peripheral OPAMP Non-Secure

Peripheral OPAMP Non-Secure

Bit 11 – CCL: Peripheral CCL Non-Secure

Peripheral CCL Non-Secure

Bit 10 – TRNG: Peripheral TRNG Non-Secure

Peripheral TRNG Non-Secure

Bit 9 – PTC: Peripheral PTC Non-Secure

Peripheral PTC Non-Secure

Bit 8 – DAC: Peripheral DAC Non-Secure

Peripheral DAC Non-Secure

Bit 7 – ADC: Peripheral ADC Non-Secure

Peripheral ADC Non-Secure

Bits 4, 5, 6 – TC: Peripheral TCn Non-Secure [n = 2..0]

Peripheral TCn Non-Secure [n = 2..0]

Bits 1, 2, 3 – SERCOM: Peripheral SERCOMn Non-Secure [n = 2..0]

Peripheral SERCOMn Non-Secure [n = 2..0]

Bit 0 – EVSYS: Peripheral EVSYS Non-Secure

Peripheral EVSYS Non-Secure