CHINTFLAG

Channel n Interrupt Flag Status and Clear

Important: For SAM L11 Non-Secure accesses, read and write accesses (RW*) are allowed only if the security attribution for the corresponding channel (CHANNELx) is set as Non-Secured in the NONSECCHAN register.
  0x26 + n*0x08 [n=0..3] 8 Mix-Secure 0x00     4 8
Parent topic: Register Description

Channel n Interrupt Flag Status and Clear

Bit  7 6 5 4 3 2 1 0  
              EVD OVR  
Access              RW/RW*/RW RW/RW*/RW  
Reset              0 0  

Bit 1 – EVD: Channel Event Detected

Channel Event Detected

This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if CHINTENCLR/SET.EVD is '1'.

When the event channel path is asynchronous, the EVD interrupt flag will not be set.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Event Detected Channel interrupt flag.

Bit 0 – OVR: Channel Overrun

Channel Overrun

This flag is set on the next CLK_EVSYS cycle after an overrun channel condition occurs, and an interrupt request will be generated if CHINTENCLR/SET.OVRx is '1'.

There are two possible overrun channel conditions:

When the event channel path is asynchronous, the OVR interrupt flag will not be set.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Overrun Channel interrupt flag.