There are two host-to-client connections to optimize system bandwidth:
- Multi-Client Hosts which are
connected through the AHB bus matrix
Table 1. AHB Multi-Client Hosts AHB Multi-Client Hosts Cortex-M23 Processor DSU - Device Service Unit DMAC - Direct Memory Access Controller / Data Access Table 2. AHB Clients AHB Clients Flash Memory AHB-APB Bridge A (APBA) AHB-APB Bridge B (APBB) AHB-APB Bridge C (APBC) SRAM Port 0 - Cortex-M23 Access SRAM Port 1 - DMAC Access SRAM Port 2 - DSU Access Boot ROM - Privileged SRAM-access Hosts
which have a direct access to some dedicated SRAM ports
Table 3. Privileged SRAM-access Hosts Privileged SRAM-access Hosts DMAC - Fetch 0 Access DMAC - Fetch 1 Access DMAC - Write Back 0 Access DMAC - Write Back 1 Access Note: Privileged SRAM-access Hosts rely on SRAM quality of service to define priority levels (SRAM Port ID). Refer to SRAM Quality of Service for more information.
Figure 1. Host-to-Client Access
