SEQCTRL0

Sequential Control 0

Note: SEQCTRL0 register is Enable-protected when CCL.LUTCTRL0.ENABLE = 1.
  0x04 8 PAC Write-Protection, Enable-protected 0x00  

Sequential Control 0

Bit  7 6 5 4 3 2 1 0  
          SEQSEL[3:0]  
Access          R/W R/W R/W R/W  
Reset          0 0 0 0  

Bits 3:0 – SEQSEL[3:0]: Sequential Selection

Sequential Selection

These bits select the sequential configuration:

Sequential Selection

ValueNameDescription
0x0 DISABLE Sequential logic is disabled
0x1 DFF D flip flop
0x2 JK JK flip flop
0x3 LATCH D latch
0x4 RS RS latch
0x5 - 0xF   Reserved