INTENSET

Interrupt Enable Set

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
  0x16 8 PAC Write-Protection 0x00  
Parent topic: Register Description

Interrupt Enable Set

Bit  7 6 5 4 3 2 1 0  
  ERROR   RXBRK CTSIC RXS RXC TXC DRE  
Access  R/W   R/W R/W R/W R/W R/W R/W  
Reset  0   0 0 0 0 0 0  

Bit 7 – ERROR: Error Interrupt Enable

Error Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.

ValueDescription
0 Error interrupt is disabled.
1 Error interrupt is enabled.

Bit 5 – RXBRK: Receive Break Interrupt Enable

Receive Break Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Receive Break Interrupt Enable bit, which enables the Receive Break interrupt.

ValueDescription
0 Receive Break interrupt is disabled.
1 Receive Break interrupt is enabled.

Bit 4 – CTSIC: Clear to Send Input Change Interrupt Enable

Clear to Send Input Change Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Clear To Send Input Change Interrupt Enable bit, which enables the Clear To Send Input Change interrupt.

ValueDescription
0 Clear To Send Input Change interrupt is disabled.
1 Clear To Send Input Change interrupt is enabled.

Bit 3 – RXS: Receive Start Interrupt Enable

Receive Start Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Receive Start Interrupt Enable bit, which enables the Receive Start interrupt.

ValueDescription
0 Receive Start interrupt is disabled.
1 Receive Start interrupt is enabled.

Bit 2 – RXC: Receive Complete Interrupt Enable

Receive Complete Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Receive Complete Interrupt Enable bit, which enables the Receive Complete interrupt.

ValueDescription
0 Receive Complete interrupt is disabled.
1 Receive Complete interrupt is enabled.

Bit 1 – TXC: Transmit Complete Interrupt Enable

Transmit Complete Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Transmit Complete Interrupt Enable bit, which enables the Transmit Complete interrupt.

ValueDescription
0 Transmit Complete interrupt is disabled.
1 Transmit Complete interrupt is enabled.

Bit 0 – DRE: Data Register Empty Interrupt Enable

Data Register Empty Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Data Register Empty Interrupt Enable bit, which enables the Data Register Empty interrupt.

ValueDescription
0 Data Register Empty interrupt is disabled.
1 Data Register Empty interrupt is enabled.