Dithering mode

Dithering is enabled by setting CTRLB.DITHER to 1. In dithering mode, DATA is a 14-bit unsigned value where DATA[13:4] is the 10-bit data converted by DAC and DATA[3:0] represents the dither bits, used for minimizing the quantization error. The principle is to make 16 sub-conversions of the DATA[13:4] value or the (DATA[13:4] + 1) value, so that by averaging those values, the conversion result of the 14-bit value (DATA[13:0]) has improved accuracy due to minimized quantization error.

To use the dithering feature, EVSYS is used for generating a periodic STARTEI. And the STARTEI event must be configured (EVCTRL.STARTEI = 1) to generate 16 events for each DATA[13:0] conversion, and DATABUFx must be loaded every 16 DAC conversions. EMPTYx event and DMA request are therefore generated every 16 DATABUF to DATA transfer. Using the DMA with dithering is optional. If the DMA is not used, it is required to poll the INTFLAG.EMTPY flag, or use an interrupt on EMPTY to add a new value in DATABUF.

The input value for DAC is positioned in the DATA register, based on CTRLB.LEFTADJ as shown in the following figure. For additional information, refer to SEQSTATUS register. If LEFTADJ = 0: the user writes DATA[13:4], and the dithering function will take care of the DATA[3:0] bit during the 16 sub-conversions.

If LEFTADJ = 1: the user writes DATA[15:6], and the dithering function will take care of the DATA[5:2] bit during the 16 sub-conversions.

Following timing diagram shows a typical example with DATA[15:0] = 0x1210, DATA[15:0] = 0x12E0, and CTRLB.LEFTADJ = 1.

Figure 1. DAC Conversions in Dithering Mode (CTRLB.LEFTADJ=1)