INTENSET

Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
  0x16 8 PAC Write-Protection 0x00  
Parent topic: Register Description - I2C Host

Interrupt Enable Set

Bit  7 6 5 4 3 2 1 0  
  ERROR           SB MB  
Access  R/W           R/W R/W  
Reset  0           0 0  

Bit 7 – ERROR: Error Interrupt Enable

Error Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.

ValueDescription
0 Error interrupt is disabled.
1 Error interrupt is enabled.

Bit 1 – SB: Client on Bus Interrupt Enable

Client on Bus Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Client on Bus Interrupt Enable bit, which enables the Client on Bus interrupt.

ValueDescription
0 The Client on Bus interrupt is disabled.
1 The Client on Bus interrupt is enabled.

Bit 0 – MB: Host on Bus Interrupt Enable

Host on Bus Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Host on Bus Interrupt Enable bit, which enables the Host on Bus interrupt.

ValueDescription
0 The Host on Bus interrupt is disabled.
1 The Host on Bus interrupt is enabled.