The following registers are enable-protected, meaning they can only be written
when the USART is disabled (CTRL.ENABLE=0):
- Control A register (CTRLA), except the
Enable (ENABLE) and Software Reset (SWRST) bits.
- Control B register (CTRLB), except the
Receiver Enable (RXEN) and Transmitter Enable (TXEN) bits.
- Baud register (BAUD)
- Control C register (CTRLC)
- Receive Pulse Length register (RXPL)
When the USART is enabled or is being enabled (CTRLA.ENABLE=1),
any writing attempt to these registers will be discarded. If the peripheral is being
disabled, writing to these registers will be executed after disabling is completed.
Enable-protection is denoted by the "Enable-Protection" property in the register
description.
Before the USART is enabled, it must be configured by
these steps:
- 1.Select either external (0x0) or internal
clock (0x1) by writing the Operating Mode value in the CTRLA register (CTRLA.MODE).
- 2.Select either asynchronous (0) or or
synchronous (1) communication mode by writing the Communication Mode bit in the CTRLA
register (CTRLA.CMODE).
- 3.Select pin for receive data by writing
the Receive Data Pinout value in the CTRLA register (CTRLA.RXPO).
- 4.Select pads for the transmitter and
external clock by writing the Transmit Data Pinout bit in the CTRLA register
(CTRLA.TXPO).
- 5.Configure the Character Size field in
the CTRLB register (CTRLB.CHSIZE) for character size.
- 6.Set the Data Order bit in the CTRLA
register (CTRLA.DORD) to determine MSB- or LSB-first data transmission.
- 7.To use parity mode:
- a.Enable parity mode by writing 0x1
to the Frame Format field in the CTRLA register (CTRLA.FORM).
- b.Configure the Parity Mode bit in
the CTRLB register (CTRLB.PMODE) for even or odd parity.
- 8.Configure the number of stop bits in the
Stop Bit Mode bit in the CTRLB register (CTRLB.SBMODE).
- 9.When using an internal clock, write the
Baud register (BAUD) to generate the desired baud rate.
- 10.Enable the transmitter and receiver by
writing '1' to the Receiver Enable and Transmitter Enable bits in the CTRLB register
(CTRLB.RXEN and CTRLB.TXEN).