CHINTENSET

Channel n Interrupt Enable Set

Important: For SAM L11 Non-Secure accesses, read and write accesses (RW*) are allowed only if the security attribution for the corresponding channel (CHANNELx) is set as Non-Secured in the NONSECCHAN register.
  0x25 + n*0x08 [n=0..3] 8 PAC Write-Protection, Mix-Secure 0x00     4 8
Parent topic: Register Description

Channel n Interrupt Enable Set

Bit  7 6 5 4 3 2 1 0  
              EVD OVR  
Access              RW/RW*/RW RW/RW*/RW  
Reset              0 0  

Bit 1 – EVD: Channel Event Detected Interrupt Enable

Channel Event Detected Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Event Detected Channel Interrupt Enable bit, which enables the Event Detected Channel interrupt.

ValueDescription
0 The Event Detected Channel interrupt is disabled.
1 The Event Detected Channel interrupt is enabled.

Bit 0 – OVR: Channel Overrun Interrupt Enable

Channel Overrun Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Overrun Channel Interrupt Enable bit, which enables the Overrun Channel interrupt.

ValueDescription
0 The Overrun Channel interrupt is disabled.
1 The Overrun Channel interrupt is enabled.