Important: For SAM
L11 Non-Secure accesses, read and
write accesses (RW*) are allowed only if the external interrupt x (EXTINTx) is set as
Non-Secure in the NONSEC register (NONSEC.EXTINTx bit). Some restrictions apply for the
Non-Secure accesses to an Enable-Protected register as it will not be possible for the
Non-Secure to configure it once this register is enabled by the Secure application. This
will require some veneers to be implemented on Secure side.
|
0x30 |
32 |
PAC Write-Protection, Enable-Protected, Mix-Secure |
0x00000000 |
|
|
Debouncer Enable
The bit x of DEBOUNCEN set the Debounce mode for the interrupt
associated with the EXTINTx pin.
Value | Description |
---|
0 |
The EXTINT x edge input is not
debounced. |
1 |
The EXTINT x edge input is
debounced. |