Peripheral Channel Control
PCHTRLm controls the settings of Peripheral Channel number m (m=0..20).
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
WRTLOCK | CHEN | GEN[2:0] | |||||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Write Lock
After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of the corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can only be unlocked by a Power Reset.
Note that Generator 0 cannot be locked.
Value | Description |
---|---|
0 | The Peripheral Channel register and the associated Generator register are not locked |
1 | The Peripheral Channel register and the associated Generator register are locked |
Channel Enable
This bit is used to enable and disable a Peripheral Channel.
Value | Description |
---|---|
0 | The Peripheral Channel is disabled |
1 | The Peripheral Channel is enabled |
Generator Selection
This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below:
Value | Description |
---|---|
0x0 | Generic Clock Generator 0 |
0x1 | Generic Clock Generator 1 |
0x2 | Generic Clock Generator 2 |
0x3 | Generic Clock Generator 3 |
0x4 | Generic Clock Generator 4 |
Reset | PCHCTRLm.GEN | PCHCTRLm.CHEN | PCHCTRLm.WRTLOCK |
---|---|---|---|
Power Reset | 0x0 | 0x0 | 0x0 |
User Reset |
If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change |
If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change |
No change |
A Power Reset will reset all the PCHCTRLm registers.
A User Reset will reset a PCHCTRL if WRTLOCK=0, or else, the content of that PCHCTRL remains unchanged.
The PCHCTRL register Reset values are shown in the table below.
index(m) | Name | Description |
---|---|---|
0 | GCLK_DPLL | FDPLL96M input clock source for reference |
1 | GCLK_DPLL_32K | FDPLL96M 32 kHz clock for FDPLL96M internal clock timer |
2 | GCLK_DFLLULP | DFLLULP clock for DFLLULP |
3 | GCLK_EIC | EIC |
4 | GCLK_FREQM_MSR | FREQM Measure |
5 | GCLK_FREQM_REF | FREQM Reference |
6 | GCLK_EVSYS_CHANNEL_0 | EVSYS_CHANNEL_0 |
7 | GCLK_EVSYS_CHANNEL_1 | EVSYS_CHANNEL_1 |
8 | GCLK_EVSYS_CHANNEL_2 | EVSYS_CHANNEL_2 |
9 | GCLK_EVSYS_CHANNEL_3 | EVSYS_CHANNEL_3 |
10 | GCLK_SERCOM[0,1,2]_SLOW | SERCOM[0,1,2]_SLOW |
11 | GCLK_SERCOM0_CORE | SERCOM0_CORE |
12 | GCLK_SERCOM1_CORE | SERCOM1_CORE |
13 | GCLK_SERCOM2_CORE | SERCOM2_CORE |
14 | GCLK_TC0, GCLK_TC1 | TC0,TC1 |
15 | GCLK_TC2 | TC2 |
16 | GCLK_ADC | ADC |
17 | GCLK_AC | AC |
18 | GCLK_DAC | DAC |
19 | GCLK_PTC | PTC |
20 | GCLK_CCL | CCL |