The RTC provides four tamper channels that can be used for tamper
detection.
The action of each tamper channel is configured using the Input n Action bits
in the Tamper Control register (TAMPCTRL.INnACT):
- Off: Detection for tamper channel
n is disabled.
- Wake: A transition on INn input
(tamper channel n) matching TAMPCTRL.TAMPLVLn will be detected and the tamper
interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will not be captured
in the TIMESTAMP register.
- Capture: A transition on INn
input (tamper channel n) matching TAMPCTRL.TAMPLVLn will be detected and the
tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will be
captured in the TIMESTAMP register.
- Active Layer Protection: A
mismatch of an internal RTC signal routed between INn and OUTn pins will be detected
and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will
be captured in the TIMESTAMP register.
In order to determine which tamper source caused a tamper event, the Tamper
ID register (TAMPID) provides the detection status of each tamper channel. These bits
remain active until cleared by software.
A single interrupt request (TAMPER) is available for all tamper
channels.
The RTC also supports an input event (TAMPEVT) for generating a tamper
condition within the Event System. The tamper input event is enabled by the Tamper Input
Event Enable bit in the Event Control register (EVCTRL.TAMPEVEI).
Up to four polarity external inputs (INn) can be used for tamper detection.
The polarity for each input is selected with the Tamper Level bits in the Tamper Control
register (TAMPCTRL.TAMPLVLn).
Separate debouncers are embedded for each external input. The debouncer for
each input is enabled/disabled with the Debounce Enable bits in the Tamper Control
register (TAMPCTRL.DEBNCn). The debouncer configuration is fixed for all inputs as set
by the Control B register (CTRLB). The debouncing period duration is configurable using
the Debounce Frequency field in the Control B register (CTRLB.DEBF). The period is set
for all debouncers (i.e., the duration cannot be adjusted separately for each
debouncer).
When TAMPCTRL.DEBNCn = 0, INn is detected asynchronously. See Edge Detection with
Debouncer Disabled below for an example.
When TAMPCTRL.DEBNCn = 1, the detection time depends on whether the debouncer operates
synchronously or asynchronously, and whether majority detection is enabled or not. Refer
to the table below for more details. Synchronous versus asynchronous stability
debouncing is configured by the Debounce Asynchronous Enable bit in the Control B
register (CTRLB.DEBASYNC):
- Synchronous (CTRLB.DEBASYNC = 0):
INn is synchronized in two CLK_RTC periods and then must remain stable for four
CLK_RTC_DEB periods before a valid detection occurs. See Edge Detection with
Synchronous Stability Debouncing below for an example.
- Asynchronous (CTRLB.DEBASYNC =
1): The first edge on INn is detected. Further detection is blanked until INn
remains stable for four CLK_RTC_DEB periods. See Edge Detection with
Asynchronous Stability Debouncing below for an example.
Majority debouncing is configured by the Debounce Majority Enable bit in the
Control B register (CTRLB.DEBMAJ). INn must be valid for two out of three CLK_RTC_DEB
periods. See
Edge Detection with Asynchronous Stability Debouncing below for an
example.
Table 1. Debouncer Configuration
TAMPCTRL. DEBNCn |
CTRLB. DEBMAJ |
CTRLB. DEBASYNC |
Description |
0 |
X |
X |
Detect edge on INn with no debouncing. Every edge
detected is immediately triggered. |
1 |
0 |
0 |
Detect edge on INn with synchronous stability
debouncing. Edge detected is only triggered when INn is stable for 4
consecutive CLK_RTC_DEB periods. |
1 |
0 |
1 |
Detect edge on INn with asynchronous stability
debouncing. First detected edge is triggered immediately. All subsequent
detected edges are ignored until INn is stable for 4 consecutive
CLK_RTC_DEB periods. |
1 |
1 |
X |
Detect edge on INn with majority debouncing. Pin INn is
sampled for 3 consecutive CLK_RTC_DEB periods. Signal level is
determined by majority-rule (LLL, LLH, LHL, HLL = '0' and LHH, HLH, HHL,
HHH = '1'). |
Figure 1. Edge Detection with Debouncer
Disabled
Figure 2. Edge Detection with Synchronous
Stability Debouncing
Figure 3. Edge Detection with Asynchronous
Stability Debouncing
Figure 4. Edge Detection with Majority
Debouncing