INTENSET

Interrupt Enable Set

Important: For SAM L11 Non-Secure accesses, read and write accesses (RW*) are allowed only if the external interrupt x (EXTINTx) is set as Non-Secure in the NONSEC register (NONSEC.EXTINTx bit).
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
  0x10 32 PAC Write-Protection, Mix-Secure 0x00000000  
Parent topic: Register Description

Interrupt Enable Set

Bit  31 30 29 28 27 26 25 24  
  NSCHK                
Access  RW/RW/RW                
Reset  0                
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
  EXTINT[7:0]  
Access  RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW  
Reset  0 0 0 0 0 0 0 0  

Bit 31 – NSCHK: Non-secure Check Interrupt Enable

Non-secure Check Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the NSCHK Interrupt Enable bit.

Bits 7:0 – EXTINT[7:0]: External Interrupt Enable

External Interrupt Enable

The bit x of EXTINT enables the interrupt associated with the EXTINTx pin.

Writing a '0' to bit x has no effect.

Writing a '1' to bit x will set the External Interrupt Enable bit x, which enables the external interrupt EXTINTx.

ValueDescription
0 The external interrupt x is disabled.
1 The external interrupt x is enabled.