APBB Mask
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HMATRIXHS | NVMCTRL | DSU | IDAU | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 1 | 1 | 1 | 1 |
HMATRIXHS APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the HMATRIXHS is stopped |
| 1 | The APBB clock for the HMATRIXHS is enabled |
NVMCTRL APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the NVMCTRL is stopped |
| 1 | The APBB clock for the NVMCTRL is enabled |
DSU APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the DSU is stopped |
| 1 | The APBB clock for the DSU is enabled |
IDAU APBB Clock Enable
| Value | Description |
|---|---|
| 0 | The APBB clock for the IDAU is stopped |
| 1 | The APBB clock for the IDAU is enabled |