Event Input Control
For each PORT group, there are up to four input event pins: EVU0-3.
Each byte of this register addresses one Event input pin.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
PORTEI3 | EVACT3[1:0] | PID3[4:0] | |||||||
Access | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
PORTEI2 | EVACT2[1:0] | PID2[4:0] | |||||||
Access | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
PORTEI1 | EVACT1[1:0] | PID1[4:0] | |||||||
Access | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PORTEI0 | EVACT0[1:0] | PID0[4:0] | |||||||
Access | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
PORT Event Input Enable x [x = 3..0]
Value | Description |
---|---|
0 | The event action x (EVACTx) will not be triggered on any incoming event. |
1 | The event action x (EVACTx) will be triggered on any incoming event. |
PORT Event Action x [x = 3..0]
These bits define the event action the PORT will perform on event input x. See also Table 1.
PORT Event Pin Identifier x [x = 3..0]
These bits define the I/O pin on which the event action will be performed, according to Table 2.
Value | Name | Description |
---|---|---|
0x0 | OUT | Output register of pin will be set to level of event. |
0x1 | SET | Set output register of pin on event. |
0x2 | CLR | Clear output register of pin on event. |
0x3 | TGL | Toggle output register of pin on event. |
Value | Name | Description |
---|---|---|
0x0 | PIN0 | Event action to be executed on PIN 0. |
0x1 | PIN1 | Event action to be executed on PIN 1. |
... | ... | ... |
0x31 | PIN31 | Event action to be executed on PIN 31. |