SRCADDR

Block Transfer Source Address

The SRCADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
  0x04 32 -    
Parent topic: Register Description - SRAM

Block Transfer Source Address

Bit  31 30 29 28 27 26 25 24  
  SRCADDR[31:24]  
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
  SRCADDR[23:16]  
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
  SRCADDR[15:8]  
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
  SRCADDR[7:0]  
Access                   
Reset                   

Bits 31:0 – SRCADDR[31:0]: Transfer Source Address

Transfer Source Address

This bit field holds the block transfer source address.

When source address incrementation is disabled (BTCTRL.SRCINC = 0), SRCADDR corresponds to the last beat transfer address in the block transfer.

When source address incrementation is enabled (BTCTRL.SRCINC = 1), SRCADDR is calculated as follows:

If BTCTRL.STEPSEL = 1:

SRCADDR=SRCADDRSTART+BTCNT⋅(BEATSIZE+1)⋅2STEPSIZE

If BTCTRL.STEPSEL = 0:

SRCADDR=SRCADDRSTART+BTCNT⋅(BEATSIZE+1)