AHB Client Bus Interrupt Flag Status and Clear
This flag is cleared by writing a '1' to the flag.
This flag is set when an access error is detected by the CLIENT n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BROM | HSRAMDSU | HSRAMDMAC | HSRAMCPU | APBC | APBB | APBA | FLASH | ||
| Access | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | RW/-/RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Interrupt Flag for Boot ROM
Interrupt Flag for CLIENT HS SRAM Port 2 - DSU Access
Interrupt Flag for CLIENT HS SRAM Port 1 - DMAC Access
Interrupt Flag for CLIENT HS SRAM Port 0 - CPU Access
Interrupt Flag for CLIENT AHB-APB Bridge C
Interrupt Flag for CLIENT AHB-APB Bridge B
Interrupt Flag for CLIENT AHB-APB Bridge A
Interrupt Flag for CLIENT FLASH