Revision History

Note: The data sheet revision is independent of the die revision (Revision bit in the Device Identification register of the Device Service Unit, DSU.DID.REVISION) and the device variant (last letter of the ordering number).

Revision G - 06/2021

In addition to the changes listed in the following table, there were numerous typographical updates that were made throughout the document.

Terminology in this document may not match with the contents of the current revision of the device errata or other Microchip documentation and collateral. If there are any questions or concerns regarding terminology, contact a Microchip support or sales representative.

The following additions or updates were done during this revision:

Section	Description
General	Throughout the entire document all references of “Master” were changed to “Host,” and “Slave” was changed to “Client,” where applicable Previous Revision histories were consolidated to clean up the flow of the document
Features	Added new information for PWM Modes using TC peripherals.
Analog Peripherals Considerations	Updated the note for Caution, and the Analog Signal Components Interconnections Diagram.
Memories	Updated Flash with a new Caution note Updated Data Flash with a new Caution note
SAM L11 Specific Security Features	Added two new figures to SAM L11 Memory Mapping Configuration Summary SAM L11 Default Memories Mapping - 64KB Flash Case SAM L11 Default Memories Mapping - 16/32KB Flash Case
Clock System	Updated the figure in On Demand Clock Requests to read CHEN instead of CLKEN
MCLK	Updated Clock Ready Flag with text regarding the CPUDIV value Updated the INTFLAG Register with new text for the CKRDY bitfield
FREQM	Updated the Block Diagram. CLK_REF is now CLK_REF_MUX. Updated CLK_REF to read CLK_REF_MUX in Principle of Operation Updated CLK_REF to read CLK_REF_MUX in Measurement
PM	Added all new text and a new caution note to SRAM Power Switch Configuration Added a caution note to the PWCFG Register, and updated the existing KB Flash tables and added new tables for 32KB and 16KB Corrected a typographical error in the INTFLAGRegister
OSCCTRL	An important note was added to External Multipurpose Crystal Oscillator (XOSC) Operation An important note was added to Clock Failure Detection Operation Replaced text in the last paragraph of Initialization, Enabling, Disabling, and Resetting Updated the XOSCCTRL Register with new text and note for the STARTUPBitfield
OSC32KCTRL	Updated Overview with new text Updated 32KHz External Crystal Oscillator (XOSC32K) Operation with a new important note Added new text and an important note to Clock Failure Detection Operation Updated bitfield descriptions in the following registers with new important notes, and new text: RTCCTRL XOSC32K
RTC	Updated the following registers with new notes: COUNT (COUNT32) COUNT (COUNT16)
DMAC	Updated the following registers with new bit alignment values: BASEADDR WRBADDR DESCADDR
PORT	Updated the figure in the Functional Description
EVSYS	Updated Sleep Mode Operation with a new note and a new row to the Event Channel Sleep Behavior Table Updated the Table 33-3. User Multiplexer Number m in the USERm register with a new description value for the AC
SERCOM	Updated I/O Lines with new text
SERCOM USART	UpdatedI/O Lineswith new text Updated the bit description for the MAXITER bit in the CTRLC Register
SERCOM SPI	Updated I/O Lines with new text Updated the DOPO bitfield with new text in the CTRLA Register
²SERCOM IC	Updated I/O Lineswith new text Updated the CTRLB Register with new bitfield access values for the CMD and QCEN bitfields
TC	Updated Capture Operations with new notes Updated Event Capture Action to read Event Capture Action on Events or I/Os, added new text and corrected capitalization in the diagram Updated Period and Pulse-Width (PPW) Capture Action to read Period and Pulse-Width (PPW/PWP) Capture Action on Events, and updated capitalization in the diagram Updated Pulse Width Capture Action to read Pulse-Width (PW) Capture Action on Events, and updated the capitalization in the diagram Updated Time Stamp Capture to read Time-Stamp Capture on Events or I/Os and removed the term Capture from the diagram Removed non-applicable text from Events Added new notes to the following registers: CTRLBCLR CTRLBSET
CCL	Updated Truth Table Inputs Selectionwith a new figure for Linked Lut Input Selection
ADC	Removed non-applicable text from Events Updated the SAMPLEN bitfield with new text and corrected the equation. A new note was added to refer to the ADC Electrical specifications. Updated the table for the REFSEL bitfield in the REFCTRL Register for the value 0x1
AC	Updated the Block Diagramto display DAC as DAC Output.
DAC	Updated the Signal Description with a new note Updated Events with a new note Updated the EVCTRL Register with new Description values for the STARTEI bitfield
OPAMP	Updated the Signal Description with a new note.
Schematic Checklist	Updated the Introduction with all new content and a caution note for a noisy environment

Revision F - 06/2020

In addition to the changes listed in the following table, there were numerous typographical updates that were made throughout the document.

The following additions or updates were done during this revision:

Section	Description
Features	Updated Silent access entries for Data Flashand TrustRAM Updated ISO7816, RS-485, and LIN Slave entries for Communication Interfaces
Configuration Summary	Added a new note to Table 1-1, SAM L10/L11 Device-Specific Features
Pinout	Moved the SERCOM related tables to the SERCOM Chapters
Memories	Updated the NVM Software Calibration Row Mapping table with new names for the 0x00 Offset
SAM L11 Specific Security Features	Updated the Note in Features Replaced NVM text in Data Flash Replaced NVM text in SRAM Added new second paragraph to Peripherals Security Attribution Removed Hardfault Generation text from Table 13-9 SAM L11 Memory Space Security Attributions Replaced the word hash with digest throughout the Crypto Acceleration chapter
Boot ROM	Updated SAM L11 Boot ROM Flow Diagram and replaced OK with Not OK Replaced the word hash with digest throughout the Boot ROM chapter
DSU	Replaced the text in SAM L11 TrustZone-Specific Register Access Updated the Register Description with new text for SAM L11 devices
MCLK	Updated the offset for the CPUDIV register
FREQM	Updated the Block Diagram and changed CLK_REF_MUX to CLK_REF
DMAC	Added new bit field description to the SRCADDR bit of the SRCADDR Register Added new bit field description to the DSTADDR bit of the DSTADDR Register
NVMCTRL	Updated the Silent Access section with new text and table
TRAM	Updated the first paragraph in Overview Updated the Silent Access section with new text and table
SERCOM	Added in the Pinout from the Pinout chapter to the Features section Added Secure Pin Multiplexing (on SERCOM) Pins (SAM L11 Only)
²SERCOM IC	Updated the Signal Description with a new note and Pinout tables
TC	Added new paragraph with information regarding the PER and PERBUF registers to Principle of Operation Replaced the NPWM and NFRQ paragraph with new text in Waveform Output Operations Updated the register property to PAC Write-Protection, Read-Synchronized, Write-Synchronized for the CTRLBSET register in 8-bit mode Updated the bit description for the PER bit for the PER Register in 8-bit mode Updated the bit description for the PER bit for thePER Register in 16-bit mode Updated the bit description for the PER bit for the PER Register in 32-bit mode
TRNG	Updated the DATA register with a new register property
ADC	Updated Calibration with new Register references of ADC BIASCOMP and BIASREFBUF Updated the BIASREFBUF andBIASCOMP bits of the CALIB register with new bit descriptions
OPAMP	Added in a new topic, Reference Buffer (REFBUF)
Electrical Characteristics at 85℃	Removed the last Equation in Analog-to-Digital Converter (ADC) Characteristics Updated Table 46-43 NVM Reliability Characteristics with a new note in NVM Characteristics Updated the FOUT drift rows converting kHz to Hz in Table 46-53 Digital Frequency Locked Loop Characteristics (LDO Regulator)
Electrical Characteristics at 125℃	Removed the last Equation in Analog-to-Digital Converter (ADC) Characteristics
AEC-Q100 Grade Electrical Characteristics	Removed the last Equation in Analog-to-Digital Converter (ADC) Characteristics Updated Table 48-22 NVM Reliability Characteristics with a new note in NVM Characteristics

Revision E - 08/2019

The following additions or updates were done during this revision:

Section	Description
Features	Added the AEC-Q100 qualifications.
Multiplexed Signals	Corrected typographical errors for note designations in the Pinout Multiplexing Table.
Peripherals Configuration Summary	Corrected typographical errors in the table.
Electrical Specifications at 85°C	Updated SERCOM in SPI Mode in PL0with new images and new equations Updated SERCOM in SPI Mode in PL2 with new images and new equations
Electrical Specifications at 125°C	Updated SERCOM in SPI Mode in PL0 with new images and new equations Updated SERCOM in SPI Mode in PL2 with new images and new equations
AEC-Q100 Electrical Specifications	This section is newly added for this release.
Package Drawings	24-pin VQFN with Stepped Wettable Flanks (AEC-Q100 Grade 1) and 32-pin VQFN with Stepped Wettable Flanks (AEC-Q100 Grade 1)

Rev D - 04/2019

Section	Updates
Features	Updated Security features
Ordering Information	Added new Ordering Information diagram to include new information for SAM L11 Securely Key Provisioned
Memories	Created new TrustRAM topic Updated NVM Software Calibration Row title from NVM Software Calibration Area. All references inside the topic have corrected the word ‘area’ to ‘row.’
Processor and Architecture	Corrected XOSCFAIL to CLKFAIL in the Interrupt Line Mapping table in Interrupt Line Mapping
Peripherals Configuration Summary	Corrected XOSCFAIL in the Peripherals Configuration Summary table to CLKFAIL Updated bit names in the User and Generator columns of the table.
SAM L11 Specific Security Features	Updated chapter title Corrected typographical and minor content errors in Features Updated Secure Pin Multiplexing on SERCOM with new content for feature enabling Updated Data Flash ScramblingChapter title from Data Flash, replaced the existing text with Data Flash scrambling information, and added a cross reference to the NVMCTRL.
Peripheral Access Controller	Updated Clocks with new CLK_PAC_AHB text The following registers were updated with corrections to register properties and bitfields: WRCTRL EVCTRL STATUSA STATUSB STATUSC NONSECA NONSECB NONSECC
GCLK	Updated Synchronization with new polling text Updated theGenerator Selection table in the PCHCTRLm register
MCLK	Updated the Peripheral Clock Default State table in Peripheral Clock Masking with new Peripheral Clock names: CLK_APBA_AHB CLK_APBB_AHB CLK_APBC_AHB CLK_HMATRIXHS_APB
FREQM	Updated the enable-protected references in the CTRLA register
PM	Updated the Register Property for the STDBYCFG Register to PAC Write-Protection
OSCCTRL	Updated Register Access Protection with DFLLULP information Corrected erroneous text in Clock Failure Detection Operation Updated the OSC16MRDY text in Interrupts and for the DPLL reference the bit names were updated with DPLLLCKR, DPLLLCKF, and DPLLLTO Updated bit names in Events, CFDEO was changed to CLKFAILEO Corrected typographical errors in Synchronization The following registers had bit names corrected,or properties updated: EVCTRL XOSCCTRL DFLLULPCTRL
OSC32KCTRL	Updated the CFD text references in Clock Failure Detection Operation Updated the EVCTRL.CLKFAILEO bit name in Events Updated CLKFAILEO in the EVCTRL register
SUPC	Corrected terminology underFeatures Updated title for Voltage Regulators System Operation Updated ‘Selecting a Voltage Regulator’ to read Selecting the Main Voltage Regulator Added new text ‘Enable-Protected (excluding BOD33.ENABLE bit)’ to theInitialization chapter Added a new bulleted item, ‘DFLLULP Low Power Voltage Reference Ready (ULPVREFRDY), asynchronous’ to Interrupts Removed BOD12 Detection reference in Events The following registers were updated to correct Register properties, bitfield names, and enable-protected text: BOD33 EVCTRL
WDT	UpdatedRegister Access Protection with a new reference to the CLEAR register Updated ENABLE bit text in Initialization Added Watchdog Clear Register (CLEAR) reference toSynchronization The following registers had updates to bitfields, properties, and enable-protection text: CTRLA CONFIG EWCTRL
RTC	Updated TAMPERID information in Register Access Protection Added new information for GP registers in Initialization Corrected bit names for CMP0-1, ALARM0, and PER0-7 inInterrupts Corrected bit names for CMP0-1, ALARM0, and PER0-7 in Events Updated the table inGeneral Purpose Registers Updated TAMPCTRL text inTamper Detection Added new Register Description topic Removed redundant text in Register Description - Mode 0 - 32-Bit Counter Removed redundant text in Register Description - Mode 1 - 16-Bit Counter Removed redundant text in Register Description - Mode 2 - Clock/Calendar The following 32 bit, 16 bit and Clock registers were updated with enable-protection text, new properties and typographical corrections: CTRLA EVCTRL SYNCBUSY GP TIMESTAMP
DMAC	Corrected bit names in Events The Not Enable-Protected attribute was updated for theCTRL register The CHCTRLB register was updated to correct a bit offset
EIC	Changed the name of the EXTINTx bit in Events to EXTINT0-7 Updated the CTRLA Register with a new Register Property Corrected a typographical error in the following registers changing Enabled-Protected to Enable-Protected: EVCTRL ASYNCH CONFIG DEBOUNCEN
NVMCTRL	Updated Overview with new bit names in the text for FLASH, Data Flash and NVM rows Removed an erroneous Note fromFeatures Removed erroneous STATUS register reference from Register Access Protection Updated Memory Organization with new bit names in the text for FLASH, Data Flash and NVM rows Updated NVM User Row (UROW) References in Region Unlock Bits Updated Command and Data Interfacewith new bit names in the text for FLASH, Data Flash and NVM rows Updated NVM Rows data in NVM Rows Operations Updated the Memory Regions and Attribute table in SAM L11 Trustzone Protections Considerations Updated text for FLASH and NVM references inLock Regions Added a new note to the Register Description The following registers were updated with corrections to properties, enable-protected text, FLASH, or bitfields: CTRLA CTRLC SCFGB SCFGAD
TRAM	References to the Data Scramble Control (DSCC) register, Permutation Write (PERMW) register, and the RAM (RAM[0:63]) addresses were removed from Register Access Protection Corrected typographical errors in Initialization The following registers had their properties updated: CTRLA STATUS SYNCBUSY PERMR
PORT - I/O Pin Controller	Updated the Cross Reference for the Nested Vector Interrupt Controller in Interrupts Updated Register Access Protection with new introductory text and a reference to the INTFLAG register Corrected typographical errors in Events Added an Event Input Pin reference to the EVCTRL register
EVSYS	Added reference to the CHINTFLAGn register in Register Access Protection Updated the register reset value on the READYUSR register Corrected multiple bit names in the Event Generators table in the CHANNELn register Corrected multiple values in the User Multiplexer Number m table of the USERm register
SERCOM	Introductory text in Register Access Protection was rephrased, and text referring to the INTFLAG, STATUS, DATA, and ADDR registers was removed Corrected typographical errors in Initialization
SERCOM - USART	Added new line item information for the CTRLC register and the RXPL register to Initialization Updated the Register property for the CTRLA Register
SERCOM - SPI	Updated the Register properties and added “these bits are not synchronized” text to the following registers: CTRLA CTRLB
²SERCOM IC	Updated Register Access Protection to remove the reference to the ADDR Register The Slave CTRLA Register was updated with a new Register property and the text “this bit is not synchronized” for the LOWTOUT bit The SlaveCTRLB Register has the register property corrected, and the text “These bits are not write synchronized,” removed The Master CTRLA Registerwas updated with a new Register Property
TC	Removed COUNT register information from Register Access Protection. Corrected the name of the Match or Capture Channel Bit from MCx to MCO-1 in Interrupts Corrected the name of the Match or Capture Channel Bit from MC0-1 to MCXO-1 in Events Added new information for Control B Clear and Control B Set Registers, and Channel x Compare/Capture Value inSynchronization Added new topics: Register Description - 8-bit Mode Register Description - 16-bit Mode Register Description - 32-bit Mode The following registers were updated: Added “This bit is not synchronized” to the COPENx bit of the CTRLA Register Updated the Register Property for the Status Register
TRNG	Updated Register Access Protectionwith new information for INTFLAG and DATA Registers.
CCL	Updated Events with new information, replacing OUTx with “LUT_n where n=0-1” Updated the Enable bit of the LUTCTRL Register with new text, “This bit is not Enable-Protected”
ADC	Updated the name of the bus clock in Clocks to CLK_ADC_APB SEQCTRLwas updated to remove an erroneous ‘n’ from the name of the Register.
AC	Updated Events to display the bit name COMP0-1, and removed information for START0 and START1 The following registers had their register properties updated: CTRLB STATUSA STATUSB SYNCBUSY
DAC	Removed EVCTRL references from Initialization Updated the Register Property for the INTFLAG Register

Rev C - 02/2019

Section	Updates
Configuration Summary	Updated SAML10/L11 Family Features
Oscillators Pinout	Updated XOSC32 Jitter Minimization
Memories	Updated NVM Software Calibration Bitfields Definition Updated SAM L11 BOCOR Bitfields Definition Updated SAM L11 BOCOR Mapping
Features	Updated Features Updated CRYA APIs Addresses with a note
Boot ROM	Updated Secure Boot Options Updated Accessible Memory Range by Read Auxiliary Row Command, and added a note
Device Service Unit (DSU)	Updated STATUSB Register
Power Manager (PM)	Updated PLCFG Register
Oscillators Controller (OSCCTRL)	Corrected missing Block Diagram Updated the reset value for the STATUS Register
32KHz Oscillators Controller (OSC32KCTRL)	Updated the ULP32KSW bit in the OSCULP32K Register
Supply Controller (SUPC)	Corrected erroneous text and added a note to Low Power VREF in Active Mode
Real Time Counter (RTC)	Updated RTC Block Diagram (Tamper Detection Use Case) Updated Active Layer Protection Updated TAMPCTRL Register with new notes for the DEBNC andTAMLVL bits Updated TAMPCTRLBRegister with a note for the ALSIbits
Direct Memory Access Controller (DMAC)	Updated the text for the DMAC Clocks section Updated the LVLEN bits for the CRTL Register Updated the LVLEX bits for the ACTIVE Register
External Interrupt Controller (EIC)	Updated the NMIFLAG Register Updated the CONFIG Register to reflect changes to the FILTEN andSENSE bits
Nonvolatile Memory Controller (NVMCTRL)	Corrected erroneous text in Cache Corrected table entries in Memory Regions AHB Access Limitations and an updated a note. Updated Data Flash Scrambling
TrustRAM (TRAM)	Corrected Erroneous text in Overview UpdatedFeatures
I/O Pin Controller (PORT)	Updated the PORTEI, EVACT, and PID bits in theEVCTRL Register
Event System (EVSYS)	Corrected text in Initialization
SERCOM USART	Updated the BAUD Register Updated the equation in the RXPL Register
²SERCOM IC	Updated Signal Description Updated the property for the slave DATA Register Updated the master DATA Register
Timer/Counter (TC)	Updated the MCEO bits in the EVCTRL Register for 8-bit, 16-bit and 32-bit Modes Updated The MC Bits in the INTENCLR, INTENSET, and INTFLAG Registers for 8-bit, 16-bit and 32-bit Modes Updated the CCBUFV bit in the STATUS Register for 8-bit, 16-bit and 32-bit Modes Updated the INVEN Bit in the DRVCTRL Register for 8-bit, 16-bit and 32-bit Modes
Configurable Custom Logic (CCL)	Updated text in Overview Updated the Block Diagram Updated the table in Signal Description Updated Linked LUT Updated Analog Comparator Inputs Removed erroneous TCC text Updated the INSEL bits in the LUTCTRL0 Register Updated the INSEL bits in the LUTCTRL1Register
Analog-to-Digital Converter (ADC)	Updated Features Updated the Block Diagram Updated the text in ADC Resolution Added a note in Oversampling and Decimation Updated the CTRLC Register
Analog Comparators (AC)	Updated the text in VDD Scaler Updated the START bits in the CTRLB Register Updated the COMPEO, COMPEI, and INVEI bits in the EVCTRL Register Updated the COMP bits in the INTENCLR, INTENSET, andINTFLAG Registers Updated the STATE bits in the STATUSA Register Updated the READY bits in the STATUSB Register Updated the COMPCTRL bits in the SYNCBUSY Register
Digital-to-Analog Converter (DAC)	Updated Features Updated Dithering Mode
Operational Amplifier Controller (OPAMP)	Updated the diagram in Offset Compensation Updated the READY bits of the STATUS Register
Electrical Characteristics	Updated the note in Absolute Maximum Ratings Removed erroneous data from the External Components Requirements in Switching Mode Table Updated the Operating Conditions Table Updated Active Current Consumption Updated Digital frequency Locked Loop Characteristics
Electrical Characteristics at 125°C	Updated “Operating Conditions Table” .
Schematic Checklist	Updated “External Analog Reference Schematic with one reference”.
Appendix A	New Section for Migrating From SAM L21 to SAM L10/L11 (32-pin Package)
Appendix B	New Section for Migrating From SAM D20/D21 to SAM L10/L11 (32-pin Package)

Rev B - 06/2018

Added new documentation for Electrical Characteristics -125°C.

Rev A - 09/2017

This is the initial released version of the document.