STATUSA

Status A

  0x0001 8 PAC Write-Protection 0x00  
Parent topic: Register Description

Status A

Bit  7 6 5 4 3 2 1 0  
      BREXT PERR FAIL BERR CRSTEXT DONE  
Access      R/W R/W R/W R/W R/W R/W  
Reset      0 0 0 0 0 0  

Bit 5 – BREXT: Boot ROM Phase Extension

Boot ROM Phase Extension

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Boot ROM Phase Extension bit.

This bit is set when a debug adapter Cold-Plugging is detected, which extends the Boot ROM phase.

Bit 4 – PERR: Protection Error

Protection Error

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Protection Error bit.

This bit is set upon access to:
  • A reserved address
  • CTRL, ADDR, LENGTH, DATA, CFG from the external address space when DAL<2
  • The internal address space with a Non-Secure access (security violation) (SAM L11 only)

Bit 3 – FAIL: Failure

Failure

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Failure bit.

This bit is set when a DSU operation failure is detected.

Bit 2 – BERR: Bus Error

Bus Error

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Bus Error bit.

This bit is set when a bus error is detected.

Bit 1 – CRSTEXT: CPU Reset Phase Extension

CPU Reset Phase Extension

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the CPU Reset Phase Extension bit.

This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase.

Bit 0 – DONE: Done

Done

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the Done bit.

This bit is set when a DSU operation is completed.