Control A
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ENABLE | SWRST | ||||||||
Access | R/W | W | |||||||
Reset | 0 | 0 |
Enable
Due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the corresponding bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the peripheral is enabled/disabled.
Value | Description |
---|---|
0 | The AC is disabled. |
1 | The AC is enabled. Each comparator must also be enabled individually by the Enable bit in the Comparator Control register (COMPCTRLn.ENABLE). |
Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the AC to their initial state, and the AC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
Value | Description |
---|---|
0 | There is no reset operation ongoing. |
1 | The reset operation is ongoing. |