CTRLA

Control A

  0x00 32 PAC Write-Protection, Enable-Protected, Write-Synchronized 0x00000000  
Parent topic: Register Description

Control A

Bit  31 30 29 28 27 26 25 24  
    LOWTOUT     SCLSM   SPEED[1:0]  
Access    R/W     R/W   R/W R/W  
Reset    0     0   0 0  
Bit  23 22 21 20 19 18 17 16  
  SEXTTOEN   SDAHOLD[1:0]       PINOUT  
Access  R/W   R/W R/W       R/W  
Reset  0   0 0       0  
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
  RUNSTDBY     MODE[2:0] ENABLE SWRST  
Access  R/W     R/W R/W R/W R/W R/W  
Reset  0     0 0 0 0 0  

Bit 30 – LOWTOUT: SCL Low Time-Out

SCL Low Time-Out

This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the client will release its clock hold, if enabled, and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set.

This bit is not synchronized.

ValueDescription
0 Time-out disabled.
1 Time-out enabled.

Bit 27 – SCLSM: SCL Clock Stretch Mode

SCL Clock Stretch Mode

This bit controls when SCL will be stretched for software interaction.

This bit is not synchronized.

ValueDescription
0 SCL stretch according to Figure 1
1 SCL stretch only after ACK bit according to Figure 2

Bits 25:24 – SPEED[1:0]: Transfer Speed

Transfer Speed

These bits define bus speed.

These bits are not synchronized.

ValueDescription
0x0 Standard-mode (Sm) up to 100 kHz and Fast-mode (Fm) up to 400 kHz
0x1 Fast-mode Plus (Fm+) up to 1 MHz
0x2 High-speed mode (Hs-mode) up to 3.4 MHz
0x3 Reserved

Bit 23 – SEXTTOEN: Client SCL Low Extend Time-Out

Client SCL Low Extend Time-Out

This bit enables the client SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the client will release its clock hold if enabled and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set. If the address was recognized, PREC will be set when a STOP is received.

This bit is not synchronized.

ValueDescription
0 Time-out disabled
1 Time-out enabled

Bits 21:20 – SDAHOLD[1:0]: SDA Hold Time

SDA Hold Time

These bits define the SDA hold time with respect to the negative edge of SCL.

These bits are not synchronized.

ValueNameDescription
0x0 DIS Disabled
0x1 75 50-100ns hold time
0x2 450 300-600ns hold time
0x3 600 400-800ns hold time

Bit 16 – PINOUT: Pin Usage

Pin Usage

This bit sets the pin usage to either two- or four-wire operation:

This bit is not synchronized.

ValueDescription
0 4-wire operation disabled
1 4-wire operation enabled

Bit 7 – RUNSTDBY: Run in Standby

Run in Standby

This bit defines the functionality in standby sleep mode.

This bit is not synchronized.

ValueDescription
0 Disabled – All reception is dropped.
1 Wake on address match, if enabled.

Bits 4:2 – MODE[2:0]: Operating Mode

Operating Mode

These bits must be written to 0x04 to select the I2C client serial communication interface of the SERCOM.

These bits are not synchronized.

Bit 1 – ENABLE: Enable

Enable

Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.

This bit is not enable-protected.

ValueDescription
0 The peripheral is disabled or being disabled.
1 The peripheral is enabled.

Bit 0 – SWRST: Software Reset

Software Reset

Writing '0' to this bit has no effect.

Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled.

Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register.

Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.

This bit is not enable-protected.

ValueDescription
0 There is no reset operation ongoing.
1 The reset operation is ongoing.