INTSTATUS

Interrupt Status

Important: For SAM L11 Non-Secure accesses, read accesses (R*) are allowed only if the security attribution for the corresponding channel (CHANNELx) is set as Non-Secured in the NONSECCHAN register.
  0x14 32 Mix-Secure 0x00000000    
Parent topic: Register Description

Interrupt Status

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
          CHINT3 CHINT2 CHINT1 CHINT0  
Access          R/R*/R R/R*/R R/R*/R R/R*/R  
Reset          0 0 0 0  

Bits 0, 1, 2, 3 – CHINTx: Channel x Pending Interrupt

Channel x Pending Interrupt

This bit is set when Channel x has a pending interrupt.

This bit is cleared when the corresponding Channel x interrupts are disabled, or the source interrupt sources are cleared.