INTENSET

Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
  0x05 8 PAC Write-Protection 0x00  
Parent topic: Register Description

Interrupt Enable Set

Bit  7 6 5 4 3 2 1 0  
        WIN0     COMP1 COMP0  
Access        R/W     R/W R/W  
Reset        0     0 0  

Bit 4 – WIN0: Window 0 Interrupt Enable

Window 0 Interrupt Enable

Reading this bit returns the state of the Window 0 interrupt enable.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit enables the Window 0 interrupt.

ValueDescription
0 The Window 0 interrupt is disabled.
1 The Window 0 interrupt is enabled.

Bits 0, 1 – COMPx: Comparator x Interrupt Enable

Comparator x Interrupt Enable

Reading this bit returns the state of the Comparator x interrupt enable.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Ready interrupt bit and enable the Ready interrupt.

ValueDescription
0 The Comparator x interrupt is disabled.
1 The Comparator x interrupt is enabled.