Power Consumption

The values in this section are measured values of power consumption under the following conditions, except where noted:

Operating Conditions
- V_DDIO = 3.3V or 1.8V
- CPU is running on Flash with required Wait states, as recommended in the NVM Characteristics section
- Low-power cache is enabled
- BOD33 is disabled
- I/Os are configured with digital input trigger disabled (default Reset configuration)
Oscillators
- XOSC (crystal oscillator) stopped
- XOSC32K (32.768 kHz crystal oscillator) running with external 32.768 kHz crystal
- When in Active mode with Performance Level 2 (PL2), DPLL is running at 32 MHz and using XOSC32K as reference
- When in Active mode on DFLLULP, the DFLLULP is configured in Closed Loop mode using XOSC32K as reference clock and MCLK.CTRLA.CKSEL = 1

Table 1. Active Current Consumption
Mode	Conditions	Regulator	PL	CPU Clock	Vcc	Ta	Typ.	Max	Units
ACTIVE	COREMARK/ FIBONACCI	LDO	PL0	DFLLULP at 8 MHz	1.8V	Max at 85°C Typ at 25°	64.1	82	μA/Mhz
				DFLLULP at 8 MHz	3.3V		64.4	84
				OSC 8 MHz	1.8V		66.6	81
				OSC 8 MHz	3.3V		70.3	83
				OSC 4 MHz	1.8V		74.1	102
				OSC 4 MHz	3.3V		77.8	106
			PL2	FDPLL96M at 32 MHz	1.8V		82.0	89
				FDPLL96M at 32 MHz	3.3V		82.5	89
				DFLLULP at 32 MHz	1.8V		75.8	99
				DFLLULP at 32 MHz	3.3V		75.8	96
		BUCK	PL0	DFLLULP at 4.88 MHz	1.8V		44	60
				DFLLULP at 4.88 MHz	3.3V		29.9	41
				OSC 8 MHz	1.8V		43.8	53
				OSC 8 MHz	3.3V		32.1	39
				OSC 4 MHz	1.8V		50.3	68
				OSC 4 MHz	3.3V		38.9	52
			PL2	FDPLL96M at 32 MHz	1.8V	Max at 85°C Typ at 25°	59.9	66
				FDPLL96M at 32 MHz	3.3V		35.3	39
				DFLLULP at 26.78 MHz	1.8V		55.8	70
				DFLLULP at 26.78 MHz	3.3V		33.7	42
	WHILE1	LDO	PL0	DFLLULP at 8 MHz	1.8V		44.3	61
				DFLLULP at 8 MHz	3.3V		44.4	62
				OSC 8 MHz	1.8V		47.6	60
				OSC 8 MHz	3.3V		50.1	63
				OSC 4 MHz	1.8V		54.6	83
				OSC 4 MHz	3.3V		57.7	86
			PL2	FDPLL96M at 32 MHz	1.8V		56.9	61
				FDPLL96M at 32 MHz	3.3V		57.2	62
				DFLLULP at 32 MHz	1.8V		50.8	66
				DFLLULP at 32 MHz	3.3V		51.0	64
ACTIVE	WHILE1	BUCK	PL0	DFLLULP at 4.88 MHz	1.8V	Max at 85°C Typ at 25°	32.4	49	μA/Mhz
				DFLLULP at 4.88 MHz	3.3V		22.8	34
				OSC 8 MHz	1.8V		32.2	41
				OSC 8 MHz	3.3V		25.3	32
				OSC 4 MHz	1.8V		38.4	57
				OSC 4 MHz	3.3V		31.9	45
			PL2	FDPLL96M at 32 MHz	1.8V		41.5	46
				FDPLL96M at 32 MHz	3.3V		24.6	28
				DFLLULP at 26.78 MHz	1.8V		38.3	48
				DFLLULP at 26.78 MHz	3.3V		23.1	29
IDLE	-	LDO	PL0	DFLLULP at 8 MHz	1.8V		16.0	32
				DFLLULP at 8 MHz	3.3V		16.2	33
				OSC 8 MHz	1.8V		19.8	33
				OSC 8 MHz	3.3V		22.0	36
				OSC 4 MHz	1.8V		26.2	55
				OSC 4 MHz	3.3V		29.2	59
			PL2	FDPLL96M at 32 MHz	1.8V		20.3	25
				FDPLL96M at 32 MHz	3.3V		20.4	26
				DFLLULP at 32 MHz	1.8V		14.3	19
				DFLLULP at 32 MHz	3.3V		14.4	19
		BUCK	PL0	DFLLULP at 4.88 MHz	1.8V		15.1	32
				DFLLULP at 4.88 MHz	3.3V		12.3	24
				OSC 8 MHz	1.8V		15.5	24
				OSC 8 MHz	3.3V		15.2	21
				OSC 4 MHz	1.8V		21.3	39
				OSC 4 MHz	3.3V		21.6	35
			PL2	FDPLL96M at 32 MHz	1.8V		14.9	19
				FDPLL96M at 32 MHz	3.3V		9.1	12
				DFLLULP at 26.78 MHz	1.8V		11.2	16
				DFLLULP at 26.78 MHz	3.3V		7.2	10

Table 2. Standby and Off Mode Current Consumption
Mode	Conditions	Regulator Mode	Vcc	Ta	Typ.	Max.	Units
STANDBY	All 16 kB RAM retained, PDSW domain in active state	LPVREG with LPEFF Disable	1.8V	25°C	1.3	3.5	µA
		LPVREG with LPEFF Disable	1.8V	85°C	18.4	66.0
		LPVREG with LPEFF Enable	3.3V	25°C	1.1	3.0
		LPVREG with LPEFF Enable	3.3V	85°C	14.2	41.8
		BUCK in standby with MAINVREG in PL0 mode (VREG.RUNSTDBY=1 and VREG.STDBYPL0=1)	1.8V	25°C	1.2	2.9
			1.8V	85°C	14.6	42.9
			3.3V	25°C	1.1	2.2
			3.3V	85°C	9.6	28.6
	All 16 kB RAM retained, PDSW domain in retention	LPVREG with LPEFF Disable	1.8V	25°C	0.6	1.1
		LPVREG with LPEFF Disable	1.8V	85°C	5.1	14.9
		LPVREG with LPEFF Enable	3.3V	25°C	0.5	1.0
		LPVREG with LPEFF Enable	3.3V	85°C	4.3	12.1
		BUCK in standby with MAINVREG in PL0 mode (VREG.RUNSTDBY=1 and VREG.STDBYPL0=1)	1.8V	25°C	0.8	1.1
			1.8V	85°C	4.3	11.9
			3.3V	25°C	0.8	1.5
			3.3V	85°C	3.4	8.5
	12 kB RAM retained,PDSW domain in retention	LPVREG with LPEFF Disable	1.8V	25°C	0.6	1.1
		LPVREG with LPEFF Disable	1.8V	85°C	4.7	13.6
		LPVREG with LPEFF Enable	3.3V	25°C	0.5	1.0
		LPVREG with LPEFF Enable	3.3V	85°C	4.0	11.1
		BUCK in standby with MAINVREG in PL0 mode (VREG.RUNSTDBY=1 and VREG.STDBYPL0=1)	1.8V	25°C	0.7	1.1
			1.8V	85°C	4.1	11.0
			3.3V	25°C	0.8	1.5
			3.3V	85°C	3.2	8.0
STANDBY	8kB RAM retained,PDSW domain in retention	LPVREG with LPEFF Disable	1.8V	25°C	0.5	1.0	µA
		LPVREG with LPEFF Disable	1.8V	85°C	4.4	12.6
		LPVREG with LPEFF Enable	3.3V	25°C	0.5	0.9
		LPVREG with LPEFF Enable	3.3V	85°C	3.8	10.3
		BUCK in standby with MAINVREG in PL0 mode (VREG.RUNSTDBY=1 and VREG.STDBYPL0=1)	1.8V	25°C	0.7	1.0
			1.8V	85°C	3.8	10.1
			3.3V	25°C	0.7	1.4
			3.3V	85°C	3.0	7.9
STANDBY	4kB RAM retained,PDSW domain in retention	LPVREG with LPEFF Disable	1.8V	25°C	0.5	0.9	µA
		LPVREG with LPEFF Disable	1.8V	85°C	4.0	11.2
		LPVREG with LPEFF Enable	3.3V	25°C	0.5	0.9
		LPVREG with LPEFF Enable	3.3V	85°C	3.5	9.3
		BUCK in standby with MAINVREG in PL0 mode (VREG.RUNSTDBY=1 and VREG.STDBYPL0=1)	1.8V	25°C	0.7	1.0
			1.8V	85°C	3.5	9.1
			3.3V	25°C	0.8	1.5
			3.3V	85°C	2.9	6.8
	4kB RAM retained,PDSW domain in retention and RTC running on XOSC32K	LPVREG with LPEFF Disable	1.8V	25°C	0.9	1.3
		LPVREG with LPEFF Disable	1.8V	85°C	4.5	11.7
		LPVREG with LPEFF Enable	3.3V	25°C	0.8	1.2
		LPVREG with LPEFF Enable	3.3V	85°C	4.0	9.8
		BUCK in standby with MAINVREG in PL0 mode (VREG.RUNSTDBY=1 and VREG.STDBYPL0=1)	1.8V	25°C	1.0	1.3
			1.8V	85°C	4.0	9.6
			3.3V	25°C	1.1	1.7
			3.3V	85°C	3.3	7.3
OFF			1.8V	25°C	34.6	54.4	nA
			1.8V	85°C	595.7	1197.3
			3.3V	25°C	61.2	89.1
			3.3V	85°C	796.1	1622.8