PRICTRL

Priority Control

  0x08 8 PAC Write-Protection, Secure 0x00  
Parent topic: Register Description

Priority Control

Bit  7 6 5 4 3 2 1 0  
  RREN           PRI[1:0]  
Access  RW/RW/RW           RW/-/RW RW/-/RW  
Reset  0           0 0  

Bit 7 – RREN: Round-Robin Scheduling Enable

Round-Robin Scheduling Enable

For details on scheduling schemes, refer to Interrupt Status and Interrupts Arbitration
ValueDescription
0 Static scheduling scheme for channels with level priority
1 Round-robin scheduling scheme for channels with level priority

Bits 1:0 – PRI[1:0]: Channel Priority Number

Channel Priority Number

When round-robin arbitration is enabled (PRICTRL.RREN=1) for priority level, this register holds the channel number of the last EVSYS channel being granted access as the active channel with priority level. The value of this bit group is updated each time the INTPEND or any of CHINTFLAG registers are written.

When static arbitration is enabled (PRICTRL.RREN=0) for priority level, and the value of this bit group is nonzero, it will not affect the static priority scheme.

This bit group is not reset when round-robin scheduling gets disabled (PRICTRL.RREN written to zero).