DPLLRATIO

DPLL Ratio Control

  0x30 32 PAC Write-Protection, Write-Synchronized 0x00000000  
Parent topic: Register Description

DPLL Ratio Control

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
          LDRFRAC[3:0]  
Access          R/W R/W R/W R/W  
Reset          0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
          LDR[11:8]  
Access          R/W R/W R/W R/W  
Reset          0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  LDR[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 19:16 – LDRFRAC[3:0]: Loop Divider Ratio Fractional Part

Loop Divider Ratio Fractional Part

Writing these bits selects the fractional part of the frequency multiplier. Due to synchronization there is a delay between writing these bits and the effect on the DPLL output clock. The value written will read back immediately and the DPLLRATIO bit in the DPLL Synchronization Busy register (DPLLSYNCBUSY.DPLLRATIO) will be set. DPLLSYNCBUSY.DPLLRATIO will be cleared when the operation is completed.

Bits 11:0 – LDR[11:0]: Loop Divider Ratio

Loop Divider Ratio

Writing these bits selects the integer part of the frequency multiplier. The value written to these bits will read back immediately, and the DPLLRATIO bit in the DPLL Synchronization busy register (DPLLSYNCBUSY.DPLLRATIO), will be set. DPLLSYNCBUSY.DPLLRATIO will be cleared when the operation is completed.