Multiplexed Signals

Each pin is controlled by the I/O Pin Controller (PORT) as a general purpose I/O and alternatively can be assigned to one of the peripheral functions: A, B, C, D, E, G, H, or I.

The following table describes the peripheral signals multiplexed to the PORT I/O pins.

The column “Reset State” indicates the reset state of the line with mnemonics:
Table 1. Pinout Multiplexing
Pin Pin Name Supply A B(1) C(2)(3) D(2)(3) E G H I Reset State
5 2 A2 1 PA00 / XIN32 VDDANA EXTINT[0]       XY[0]   OA1NEG   SERCOM1/PAD[0] TC2/WO[0]       I/O, Hi-Z
6 3 A3 2 PA01 / XOUT32 VDDANA EXTINT[1]       XY[1]   OA1POS   SERCOM1/PAD[1] TC2/WO[1]       I/O, Hi-Z
7 4 A4 3 PA02 VDDANA EXTINT[2]   AIN[0]   XY[2] VOUT OA0NEG   SERCOM0/PAD[2]         I/O, Hi-Z
8 5 B3 4 PA03 VDDANA EXTINT[3] VREFA AIN[1]   XY[3]   OA2NEG   SERCOM0/PAD[3]         I/O, Hi-Z
9 6 B4 5 PA04 VDDANA EXTINT[4] VREFB AIN[2] AIN[0]     OA2OUT   SERCOM0/PAD[0] TC0/WO[0]     IN[0] I/O, Hi-Z
10 7 A5 6 PA05 VDDANA EXTINT[5]   AIN[3] AIN[1] XY[4]   OA2POS   SERCOM0/PAD[1] TC0/WO[1]     IN[1] I/O, Hi-Z
    C4 7 PA06 VDDANA EXTINT[6]   AIN[4] AIN[2] XY[5]   OA0POS   SERCOM0/PAD[2] TC1/WO[0]     IN[2] I/O, Hi-Z
    B5 8 PA07 VDDANA EXTINT[7]   AIN[5] AIN[3]     OA0OUT   SERCOM0/PAD[3] TC1/WO[1]     OUT[0] I/O, Hi-Z
11 8 B6 9 VDDANA                             -
12 9 C6 10 GNDANA                             -
13 10 D4 11 PA08 VDDIO NMI   AIN[6]   XY[6]     SERCOM1/PAD[0] SERCOM2/PAD[0]   RTC/IN[0]   IN[3] I/O, Hi-Z
    D6 12 PA09 VDDIO EXTINT[0]   AIN[7]   XY[7]     SERCOM1/PAD[1] SERCOM2/PAD[1]   RTC/IN[1]   IN[4] I/O, Hi-Z
    C5 13 PA10 VDDIO EXTINT[1]   AIN[8]   XY[8]     SERCOM1/PAD[2] SERCOM2/PAD[2]     GCLK_IO[4] IN[5] I/O, Hi-Z
    D5 14 PA11 VDDIO EXTINT[2]   AIN[9]   XY[9]     SERCOM1/PAD[3] SERCOM2/PAD[3]     GCLK_IO[3] OUT[1] I/O, Hi-Z
14 11 E6 15 PA14 / XOSC VDDIO EXTINT[3]       XY[10]     SERCOM2/PAD[2] SERCOM0/PAD[2] TC0/WO[0]   GCLK_IO[0]   I/O, Hi-Z
15 12 E5 16 PA15 / XOUT VDDIO EXTINT[4]       XY[11]     SERCOM2/PAD[3] SERCOM0/PAD[3] TC0/WO[1]   GCLK_IO[1]   I/O, Hi-Z
16 13 D3 17 PA16(4) VDDIO EXTINT[5]       XY[12]     SERCOM1/PAD[0] SERCOM0/PAD[0]   RTC/IN[2] GCLK_IO[2] IN[0] I/O, Hi-Z
17 14 F5 18 PA17(4) VDDIO EXTINT[6]       XY[13]     SERCOM1/PAD[1] SERCOM0/PAD[1]   RTC/IN[3] GCLK_IO[3] IN[1] I/O, Hi-Z
18 15 E4 19 PA18 VDDIO EXTINT[7]       XY[14]     SERCOM1/PAD[2] SERCOM0/PAD[2] TC2/WO[0] RTC/OUT[0] AC/CMP[0] IN[2] I/O, Hi-Z
19 16 E3 20 PA19 VDDIO EXTINT[0]       XY[15]     SERCOM1/PAD[3] SERCOM0/PAD[3] TC2/WO[1] RTC/OUT[1] AC/CMP[1] OUT[0] I/O, Hi-Z
20 17 F4 21 PA22(4) VDDIO EXTINT[1]       XY[16]     SERCOM0/PAD[0] SERCOM2/PAD[0] TC0/WO[0] RTC/OUT[2] GCLK_IO[2]   I/O, Hi-Z
21 18 F3 22 PA23(4) VDDIO EXTINT[2]       XY[17]     SERCOM0/PAD[1] SERCOM2/PAD[1] TC0/WO[1] RTC/OUT[3] GCLK_IO[1]   I/O, Hi-Z
    F2 23 PA24 VDDIO EXTINT[3]             SERCOM0/PAD[2] SERCOM2/PAD[2] TC1/WO[0]       I/O, Hi-Z
    E2 24 PA25 VDDIO EXTINT[4]             SERCOM0/PAD[3] SERCOM2/PAD[3] TC1/WO[1]       I/O, Hi-Z
    D2 25 PA27 VDDIO EXTINT[5]                     GCLK_IO[0]   I/O, Hi-Z
22 19 C2 26 RESET VDDIO                           I, PU
23 20 E1 27 VDDCORE                             -
24 21 D1 28 GND                             -
1 22 C1 29 VDDOUT                             -
2 23 B1 30 VDDIO                             -
3 24 B2 31 PA30 / SWCLK VDDIO EXTINT[6]       XY[18]       SERCOM1/PAD[2] TC1/WO[0] SWCLK GCLK_IO[0] IN[3] SWCLK, I, PU
4 1 C3 32 PA31 / SWDIO(4) VDDIO EXTINT[7]       XY[19]       SERCOM1/PAD[3] TC1/WO[1]     OUT[1] I/O, Hi-Z
  1. 1.All analog pin functions are on the peripheral function B. The peripheral function B must be selected to disable the digital control of the pin.
  2. 2.Refer to SERCOM Features to get the list of the supported features for each SERCOM instance.
  3. 3.24-pin packages only have two SERCOM instances: SERCOM0 and SERCOM1.
  4. 4.The following pins are High Sink pins and have different properties than standard pins: PA16, PA17, PA22, PA23 and PA31.