DFLLULPDLY

DFLLULP Delay Value

  0x20 32 PAC Write-Protection, Write-Synchronized 0x00000080    
Parent topic: Register Description

DFLLULP Delay Value

Bit  31 30 29 28 27 26 25 24  
                   
Access                   
Reset                   
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
  DELAY[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  1 0 0 0 0 0 0 0  

Bits 7:0 – DELAY[7:0]: Delay Value

Delay Value

Writing a value to this field sets the oscillator delay. A small value will produce a fast clock and a large value will produce a slow clock. Writing to this field will cause the tuner to start tuning from the written value. Reading this value will return the last written delay or the oscillator delay when a synchronization was requested from the DFLLULPRREQ register. Writing a value to this register while a write synchronization or a read request synchronization is on-going will have no effect and produce a PAC error.