COUNT

Counter Value, 32-bit Mode

Note: Prior to any read access, this register must be synchronized by user by writing the according TC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
  0x14 32 PAC Write-Protection, Write-Synchronized, Read-Synchronized 0x00  
Parent topic: Register Description - 32-bit Mode

Counter Value, 32-bit Mode

Bit  31 30 29 28 27 26 25 24  
  COUNT[31:24]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  COUNT[23:16]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  COUNT[15:8]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  COUNT[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 31:0 – COUNT[31:0]: Counter Value

Counter Value

These bits contain the current counter value.