Write Configuration
This write-only register is used to configure several pins simultaneously with the same configuration and/or peripheral multiplexing.
In order to avoid side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect. Reading this register always returns zero.
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
HWSEL | WRPINCFG | WRPMUX | PMUX[3:0] | ||||||
Access | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
DRVSTR | PULLEN | INEN | PMUXEN | ||||||
Access | W/W*/W | W/W*/W | W/W*/W | W/W*/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
PINMASK[15:8] | |||||||||
Access | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PINMASK[7:0] | |||||||||
Access | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | W/W*/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Half-Word Select
This bit selects the half-word field of a 32-PORT group to be reconfigured in the atomic write operation.
This bit will always read as zero.
Value | Description |
---|---|
0 | The lower 16 pins of the PORT group will be configured. |
1 | The upper 16 pins of the PORT group will be configured. |
Write Pin Configuration Register (PINCFGy)
This bit determines whether the atomic write operation will update the Pin Configuration register (PINCFGy) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.
Writing '0' to this bit has no effect.
Writing '1' to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR, WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN, and WRCONFIG.PINMASK values.
This bit will always read as zero.
Value | Description |
---|---|
0 | The PINCFGy registers of the selected pins will not be updated. |
1 | The PINCFGy registers of the selected pins will be updated. |
Write Peripheral Multiplexing Register (PMUXn)
This bit determines whether the atomic write operation will update the Peripheral Multiplexing register (PMUXn) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.
Writing '0' to this bit has no effect.
Writing '1' to this bit updates the pin multiplexer configuration of the selected pins with the written WRCONFIG.PMUX value.
This bit will always read as zero.
Value | Description |
---|---|
0 | The PMUXn registers of the selected pins will not be updated. |
1 | The PMUXn registers of the selected pins will be updated. |
Peripheral Multiplexing
These bits determine the new value written to the Peripheral Multiplexing register (PMUXn) for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPMUX bit is set.
These bits will always read as zero.
Output Driver Strength Selection
This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Pull Enable
This bit determines the new value written to PINCFGy.PULLEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Input Enable
This bit determines the new value written to PINCFGy.INEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Peripheral Multiplexer Enable
This bit determines the new value written to PINCFGy.PMUXEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.
This bit will always read as zero.
Pin Mask for Multiple Pin Configuration
These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit.
These bits will always read as zero.
Value | Description |
---|---|
0 | The configuration of the corresponding I/O pin in the half-word group will be left unchanged. |
1 | The configuration of the corresponding I/O pin in the half-word PORT group will be updated. |