WRCONFIG

Write Configuration

Important: For SAM L11 Non-Secure accesses, write accesses (W*) are allowed only if the security attribution for the corresponding I/O pin is set as Non-Secured in the NONSEC register.
Tip: The I/O pins are assembled in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group 1 is for the PB pins, etc. Each pin group has its own PORT registers, with a 0x80 address spacing. For example, the register address offset for the Data Direction (DIR) register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR register for group 1 (PB00 to PB31) is 0x80.

This write-only register is used to configure several pins simultaneously with the same configuration and/or peripheral multiplexing.

In order to avoid side effect of non-atomic access, 8-bit or 16-bit writes to this register will have no effect. Reading this register always returns zero.

  0x28 32 PAC Write-Protection, Mix-Secure 0x00000000  
Parent topic: Register Description

Write Configuration

Bit  31 30 29 28 27 26 25 24  
  HWSEL WRPINCFG   WRPMUX PMUX[3:0]  
Access  W/W*/W W/W*/W   W/W*/W W/W*/W W/W*/W W/W*/W W/W*/W  
Reset  0 0   0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
    DRVSTR       PULLEN INEN PMUXEN  
Access    W/W*/W       W/W*/W W/W*/W W/W*/W  
Reset    0       0 0 0  
Bit  15 14 13 12 11 10 9 8  
  PINMASK[15:8]  
Access  W/W*/W W/W*/W W/W*/W W/W*/W W/W*/W W/W*/W W/W*/W W/W*/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  PINMASK[7:0]  
Access  W/W*/W W/W*/W W/W*/W W/W*/W W/W*/W W/W*/W W/W*/W W/W*/W  
Reset  0 0 0 0 0 0 0 0  

Bit 31 – HWSEL: Half-Word Select

Half-Word Select

This bit selects the half-word field of a 32-PORT group to be reconfigured in the atomic write operation.

This bit will always read as zero.

ValueDescription
0 The lower 16 pins of the PORT group will be configured.
1 The upper 16 pins of the PORT group will be configured.

Bit 30 – WRPINCFG: Write Pin Configuration Register (PINCFGy)

Write Pin Configuration Register (PINCFGy)

This bit determines whether the atomic write operation will update the Pin Configuration register (PINCFGy) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.

Writing '0' to this bit has no effect.

Writing '1' to this bit updates the configuration of the selected pins with the written WRCONFIG.DRVSTR, WRCONFIG.PULLEN, WRCONFIG.INEN, WRCONFIG.PMUXEN, and WRCONFIG.PINMASK values.

This bit will always read as zero.

ValueDescription
0 The PINCFGy registers of the selected pins will not be updated.
1 The PINCFGy registers of the selected pins will be updated.

Bit 28 – WRPMUX: Write Peripheral Multiplexing Register (PMUXn)

Write Peripheral Multiplexing Register (PMUXn)

This bit determines whether the atomic write operation will update the Peripheral Multiplexing register (PMUXn) or not for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits.

Writing '0' to this bit has no effect.

Writing '1' to this bit updates the pin multiplexer configuration of the selected pins with the written WRCONFIG.PMUX value.

This bit will always read as zero.

ValueDescription
0 The PMUXn registers of the selected pins will not be updated.
1 The PMUXn registers of the selected pins will be updated.

Bits 27:24 – PMUX[3:0]: Peripheral Multiplexing

Peripheral Multiplexing

These bits determine the new value written to the Peripheral Multiplexing register (PMUXn) for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPMUX bit is set.

These bits will always read as zero.

Bit 22 – DRVSTR: Output Driver Strength Selection

Output Driver Strength Selection

This bit determines the new value written to PINCFGy.DRVSTR for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.

This bit will always read as zero.

Bit 18 – PULLEN: Pull Enable

Pull Enable

This bit determines the new value written to PINCFGy.PULLEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.

This bit will always read as zero.

Bit 17 – INEN: Input Enable

Input Enable

This bit determines the new value written to PINCFGy.INEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.

This bit will always read as zero.

Bit 16 – PMUXEN: Peripheral Multiplexer Enable

Peripheral Multiplexer Enable

This bit determines the new value written to PINCFGy.PMUXEN for all pins selected by the WRCONFIG.PINMASK and WRCONFIG.HWSEL bits, when the WRCONFIG.WRPINCFG bit is set.

This bit will always read as zero.

Bits 15:0 – PINMASK[15:0]: Pin Mask for Multiple Pin Configuration

Pin Mask for Multiple Pin Configuration

These bits select the pins to be configured within the half-word group selected by the WRCONFIG.HWSEL bit.

These bits will always read as zero.

ValueDescription
0 The configuration of the corresponding I/O pin in the half-word group will be left unchanged.
1 The configuration of the corresponding I/O pin in the half-word PORT group will be updated.