INTFLAG

Interrupt Flag Status and Clear

Important: For SAM L11 Non-Secure accesses, read and write accesses (RW*) are allowed only if the external interrupt x (EXTINTx) is set as Non-Secure in the NONSEC register (NONSEC.EXTINTx bit).
  0x14 32 Mix-Secure 0x00000000  
Parent topic: Register Description

Interrupt Flag Status and Clear

Bit  31 30 29 28 27 26 25 24  
  NSCHK                
Access  RW/RW/RW                
Reset  0                
Bit  23 22 21 20 19 18 17 16  
                   
Access                   
Reset                   
Bit  15 14 13 12 11 10 9 8  
                   
Access                   
Reset                   
Bit  7 6 5 4 3 2 1 0  
  EXTINT[7:0]  
Access  RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW RW/RW*/RW  
Reset  0 0 0 0 0 0 0 0  

Bit 31 – NSCHK: Non-secure Check Interrupt

Non-secure Check Interrupt

The flag is cleared by writing a '1' to it. This flag is set when write to either NONSEC and NSCHK register and if the related bit of NSCHK is enabled and the related bit of NONSEC is zero.

Bits 7:0 – EXTINT[7:0]: External Interrupt

External Interrupt

The flag bit x is cleared by writing a '1' to it.

This flag is set when EXTINTx pin matches the external interrupt sense configuration and will generate an interrupt request if INTENCLR.EXTINT[x] or INTENSET.EXTINT[x] is '1'.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit clears the External Interrupt x flag.