CCx

Channel x Compare/Capture Value, 32-bit Mode

  0x1C + x*0x04 [x=0..1] 32 Write-Synchronized 0x00000000   2 -1
Parent topic: Register Description - 32-bit Mode

Channel x Compare/Capture Value, 32-bit Mode

Bit  31 30 29 28 27 26 25 24  
  CC[31:24]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  23 22 21 20 19 18 17 16  
  CC[23:16]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  15 14 13 12 11 10 9 8  
  CC[15:8]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  
Bit  7 6 5 4 3 2 1 0  
  CC[7:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 31:0 – CC[31:0]: Channel x Compare/Capture Value

Channel x Compare/Capture Value

These bits contain the compare/capture value in 32-bit TC mode. In Match frequency (MFRQ) or Match PWM (MPWM) waveform operation (WAVE.WAVEGEN), the CC0 register is used as a period register.