Channel Status
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FERR | BUSY | PEND | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
Channel Fetch Error
This bit is cleared when a software resume command is executed.
This bit is set when an invalid descriptor is fetched.
Channel Busy
This bit is cleared when the channel trigger action is completed, when a bus error is detected or when the channel is disabled.
This bit is set when the DMA channel starts a DMA transfer.
Channel Pending
This bit is cleared when the channel trigger action is started, when a bus error is detected or when the channel is disabled. For details on trigger action settings, refer to CHCTRLB.TRIGACT.
This bit is set when a transfer is pending on the DMA channel, as soon as the transfer request is received.