In I2C Sm, Fm, and
Fm+ mode, the Host clock (SCL) frequency is determined as described in this
section:
The low (TLOW) and high (THIGH)
times are determined by the Baud Rate register (BAUD), while the rise (TRISE) and fall (TFALL) times are determined by the
bus topology. Because of the wired-AND logic of the bus, TFALL will be considered as part of TLOW. Likewise, TRISE will be in a state between
TLOW and THIGH until a high state has been
detected.
Figure 1. SCL Timing
The following parameters are timed using
the SCL low time period T
LOW. This comes from the Host
Baud Rate Low bit group in the Baud Rate register (BAUD.BAUDLOW). When BAUD.BAUDLOW=0, or
the Host Baud Rate bit group in the Baud Rate register (BAUD.BAUD) determines it.
- TLOW – Low period of SCL clock
- TSU;STO – Set-up time for stop condition
- TBUF – Bus free time between stop and start
conditions
- THD;STA – Hold time (repeated) start condition
- TSU;STA – Set-up time for repeated start
condition
- THIGH is timed using the SCL high time count from
BAUD.BAUD
- TRISE is determined by the bus impedance; for
internal pull-ups.
- TFALL is determined by the open-drain current limit
and bus impedance; can typically be regarded as zero.
The SCL frequency is given by:
fSCL=1TLOW+THIGH+TRISE
When BAUD.BAUDLOW is zero, the BAUD.BAUD
value is used to time both SCL high and SCL low. In this case the following formula will
give the SCL frequency:
fSCL=fGCLK10+ 2BAUD+fGCLK⋅TRISE
When BAUD.BAUDLOW is non-zero, the
following formula determines the SCL frequency:
fSCL=fGCLK10+ BAUD+BAUDLOW+fGCLK⋅TRISE
The following formulas can determine the
SCL TLOW and THIGH times:
TLOW=BAUDLOW+5fGCLK
THIGH=BAUD+5fGCLK
Note: The I2C standard Fm+ (Fast-mode plus) requires a nominal high to
low SCL ratio of 1:2, and BAUD should be set accordingly. At a minimum, BAUD.BAUD and/or
BAUD.BAUDLOW must be non-zero.
Startup Timing The minimum time between SDA transition and SCL rising edge is 6 APB
cycles when the DATA register is written in smart mode. If a greater startup time is
required due to long rise times, the time between DATA write and IF clear must be
controlled by software.
Note: When timing is controlled by user, the Smart Mode cannot be
enabled.