Peripheral and Embedded Hard Blocks

Various features of the architecture are located within the periphery but are not available within the FPGA array. These features can be incorporated within a block design but must be carefully enclosed to all the feature's I/Os within the block. Such features for PolarFire design are listed below:

Note:

While checking these interfaces in Chip Planner, flyline connections could converge at a single co-ordination.

A large bus structure spread across an area is seen in the Chip Planner when the actual routing is viewed. If any I/O has an external name, off the chip, then it must be the same port name as in the top-level of the design.