Start, Stop and Reset Events

To enable the counter/timer, the ON bit of the TUxyCON0 register must be set. When ON = 0, the module is disabled, and the module output is cleared.
When the module is disabled, the following things apply:
  1. 1.RUN SFR bit is cleared.
  2. 2.OPOL bit in the TUxyCON0 register will continue to control the output polarity.
  3. 3.ERS input logic is reset and disabled.
  4. 4.Interrupts will not trigger.
  5. 5.Clock requests are not asserted.
  6. 6.All SFRs can be written.
Important:
  1. 1.The value of the TUxyTMR counter and TUxyCR capture registers are not affected when the ON bit is clear, unless they are changed explicitly by the user.
  2. 2.Clock synchronization may apply, in which case, actions performed may or may not have immediate effect.
  3. 3.The ON bit, like many other bits in the module, remains unchanged after a non-POR/BOR system Reset. It is recommended to clear the ON bit at the start of program execution to avoid starting the system with a running timer.