Extended Instruction Set

Important: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes:

{label} instruction argument(s)

ADDULNK Add Literal to FSR2 and Return
Syntax ADDULNK k
Operands

0 ≤ k ≤ 63

Operation

(FSR2) + k → FSR2
(TOS) → PC

Status Affected None
Encoding 1110 1000 11kk kkkk
Description

The 6-bit literal ‘k’ is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where fn = 3 (binary ‘11’); it operates only on FSR2.

Words 1
Cycles 2

Q Cycle Activity:

Q1 Q2 Q3 Q4
Decode Read literal ‘k’ Process Data Write to destination
No operation No operation No operation No operation

Example: ADDULNK 23h

Before Instruction
FSR2 = 03FFh
PC = 0100h

After Instruction
FSR2 = 0422h
PC = (TOS)

MOVSF Move Indexed to f
Syntax MOVSF [zs], fd
Operands

0 ≤ zs ≤ 127
0 ≤ fd ≤ 4095

Operation

((FSR2) + zs) → fd

Status Affected None
Encoding 1110 1011 0zszszs zszszszs
1111 fdfdfdfd fdfdfdfd fdfdfdfd
Description

The contents of the source register are moved to destination register ‘fd’. The actual address of the source register is determined by adding the 7-bit literal offset ‘zs’ in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal ‘fd’ in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh).

Note:

MOVSF has curtailed the destination range to the lower 4 Kbyte space in memory (Banks 1 through 15). For everything else, use MOVSFL.

Words 2
Cycles 2

Q Cycle Activity:

Q1 Q2 Q3 Q4
Decode Determine source address Determine source address Read source register
Decode

No operation
No dummy read

No operation Write register ‘fd

Example: MOVSF [05h], REG2

Before Instruction
FSR2 = 80h
Contents of 85h = 33h
REG2 = 11h
Address of REG2 = 100h

After Instruction
FSR2 = 80h
Contents of 85h = 33h
REG2 = 33h
Address of REG2 = 100h

MOVSFL Move Indexed to f (Long Range)
Syntax MOVSFL [zs], fd
Operands

0 ≤ zs ≤ 127
0 ≤ fd ≤ 16383

Operation

((FSR2) + zs) → fd

Status Affected None
Encoding 0000 0000 0110 0010
1111 xxxzs zszszszs zszsfdfd
1111 fdfdfdfd fdfdfdfd fdfdfdfd
Description

The contents of the source register are moved to destination register ‘fd’. The actual address of the source register is determined by adding the 7-bit literal offset ‘zs’ in the first word to the value of FSR2 (14 bits). The address of the destination register is specified by the 14-bit literal ‘fd’ in the second word. Both addresses can be anywhere in the 16 Kbyte data space (0000h to 3FFFh). The MOVSFL instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h.

Words 3
Cycles 3

Q Cycle Activity:

Q1 Q2 Q3 Q4
Decode No operation No operation No operation
Decode Read source register Process Data No operation
Decode

No operation
No dummy read

No operation Write register ‘fd

Example: MOVSFL [05h], REG2

Before Instruction
FSR2 = 2080h
Contents of 2085h = 33h
REG2 = 11h
Address of REG2 = 2000h

After Instruction
FSR2 = 2080h
Contents of 2085h = 33h
REG2 = 33h
Address of REG2 = 2000h

MOVSS Move Indexed to Indexed
Syntax MOVSS [zs], [zd]
Operands

0 ≤ zs ≤ 127
0 ≤ zd ≤ 127

Operation

((FSR2) + zs) → ((FSR2) + zd)

Status Affected None
Encoding 1110 1011 1zszszs zszszszs
1111 xxxx xzdzdzd zdzdzdzd
Description

The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets ‘zs’ or ‘zd’ respectively to the value of FSR2. Both registers can be located anywhere in the 16 Kbyte data memory space (0000h to 3FFFh).

The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register.

If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP.

Words 2
Cycles 2

Q Cycle Activity:

Q1 Q2 Q3 Q4
Decode Determine source address Determine source address Read source register
Decode Determine destination address Determine destination address Write to destination register

Example: MOVSS [05h], [06h]

Before Instruction
FSR2 = 80h
Contents of 85h = 33h
Contents of 86h = 11h

After Instruction
FSR2 = 80h
Contents of 85h = 33h
Contents of 86h = 33h

PUSHL Store Literal at FSR2, Decrement FSR2
Syntax PUSHL k
Operands

0 ≤ k ≤ 255

Operation

k → FSR2
(FSR2) – 1 → FSR2

Status Affected None
Encoding 1111 1010 kkkk kkkk
Description

The 8-bit literal ‘k’ is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack.

Words 1
Cycles 1

Q Cycle Activity:

Q1 Q2 Q3 Q4
Decode Read literal ‘k’ Process Data Write to destination

Example: PUSHL 08h

Before Instruction
FSR2 = 01ECh
Contents of 01ECh = 00h

After Instruction
FSR2 = 01EBh
Contents of 01ECh = 08h

SUBULNK Subtract Literal from FSR2 and Return
Syntax SUBULNK k
Operands

0 ≤ k ≤ 63

Operation

(FSR2) – k → FSR2
(TOS) → PC

Status Affected None
Encoding 1110 1001 11kk kkkk
Description

The 6-bit literal ‘k’ is subtracted from the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where fn = 3 (binary ‘11’); it operates only on FSR2.

Words 1
Cycles 2

Q Cycle Activity:

Q1 Q2 Q3 Q4
Decode Read literal ‘k’ Process Data Write to destination
No operation No operation No operation No operation

Example: SUBULNK 23h

Before Instruction
FSR2 = 03FFh
PC = 0100h

After Instruction
FSR2 = 03DCh
PC = (TOS)