I3CxMWS

I3CxMWS

Maximum Write Speed

Note:
  1. 1.This register follows the definition of GETMXDS CCC Maximum Write Speed Byte format as per the MIPI I3C Basic 1.0 Specification. The Controller can read this byte during GETMXDS CCC.
0x0AB, 0x0DC 8     1index x
Parent topic: Register Definitions: I3C Control

I3CxMWS

Bit  7 6 5 4 3 2 1 0  
  MWS[7:3] MWS[2:0]  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 9:3 – MWS[7:3]: MIPI Reserved

MIPI Reserved

Bits 2:0 – MWS[2:0]: Maximum Write Speed for Non-CCC Messages

Maximum Write Speed for Non-CCC Messages

ValueDescription
111 MIPI Reserved
110 MIPI Reserved
101 MIPI Reserved
100 2 MHz
011 4 MHz
010 6 MHz
001 8 MHz
000 FSCL Max