SDA and SCL Pins

Similar to I2C, the I3C bus consists of a serial data line (SDA) and a serial clock line (SCL), although the bus voltage, frequency, and signaling may vary. Refer to Table 1 for more information.

The I3C SDA and SCL pins on this device are in a separated voltage domain powered by the Multi-Voltage I/O (MVIO). The VDDIOx power pin corresponding to the SDA/SCL pins must be powered up to the desired operating voltage level for the device to be present on the I3C bus. Refer to the “MVIO – Multi-Voltage I/O” chapter for more information.

CAUTION: When the I3C module is enabled, the SDA and SCL pads support a maximum voltage of 3.63V. The voltage on the corresponding VDDIOx power pin should not exceed this limit when I3C is enabled to prevent the risk of damaging the device. However, the pins can support higher voltages when the I3C module is disabled. Refer to “Electrical Specifications” chapter for details.

The I3C SDA and SCL pins must be configured as open-drain outputs. Open-drain configuration is accomplished by setting the appropriate bits in the Open-Drain Control (ODCONx) registers, while the output direction is handled by clearing the appropriate bits in the Tri-State Control (TRISx) registers. Refer to the “I/O Ports” chapter for more information.

This device is equipped with fail-safe I3C pads for SDA and SCL lines which are designed to avoid drawing current from the I3C bus when connected and the I3C bus is powered off. The I3C SDA and SCL pads are equipped with the following buffers:

The following sections define how to select the appropriate buffers for user application.

Important: The pin locations for I3C SDA and SCL are not remappable through the Peripheral Pin Select (PPS) registers on this device. The I3C module on these devices uses dedicated SDA and SCL pads that can meet the I3C speed requirements and are capable of using the I3C Low-Voltage Buffers for communication.
Figure 1. Pad Buffer Selection for I3C® Mode Operation Across Supported Voltage Range
Figure 2. Pad Buffer Selection for I2C Mode Operation
Table 1. Available Buffer Selections for I3C SDR and I2C/SMBus Modes of Operation of the I3C® Module
Available Pad Buffers I3C® SDR Mode Operation I2C/SMBus Mode Operation

I3C Low-Voltage Buffers

(selectable through IOLVCON)
Yes No

I2C/SMBus Buffers

(selectable through RxyI2C.TH)
No Yes

ST/TTL Buffers

(selectable through RxyI2C.TH and INLVLx)
ST Buffers only (Enabling I3C module through I3CxCON.EN disables the TTL Buffers)(1)
Note: ST Buffers are not functional below 1.62V. When the VDDIOx voltage drops below 1.62V, the I3C Low-Voltage Buffers are auto enabled if the bandgap reference is already enabled.