IOCxN

IOCxN

Interrupt-on-Change Negative Edge Register Example
Important:
  • If MCLRE = 1 or LVP = 1, the MCLR pin port functionality is disabled and IOC on that pin is not available
  • Refer to the “Pin Allocation Table” for details about pins with configurable IOC per port
    8  

IOCxN

Bit  7 6 5 4 3 2 1 0  
  IOCxN7 IOCxN6 IOCxN5 IOCxN4 IOCxN3 IOCxN2 IOCxN1 IOCxN0  
Access  R/W R/W R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCxNn: Interrupt-on-Change Negative Edge Enable

Interrupt-on-Change Negative Edge Enable

ValueDescription
1 Interrupt-on-change enabled on the IOCx pin for a negative-going edge. Associated Status bit and interrupt flag will be set upon detecting an edge.
0 Falling edge interrupt-on-change disabled for the associated pin