UxCON2

UxCON2

UART Control Register 2
Notes:
  1. 1.All modes transmit selected number of Stop bits.
  2. 2.Full-featured UARTs only.
    8    

UxCON2

Bit  7 6 5 4 3 2 1 0  
  RUNOVF RXPOL STP[1:0] C0EN TXPOL FLO[1:0]  
Access  R/W R/W/HC R/W R/W R/W R/W R/W R/W  
Reset  0 0 0 0 0 0 0 0  

Bit 7 – RUNOVF: Run During Overflow Control

Run During Overflow Control

ValueDescription
1 RX input shifter continues to synchronize with Start bits after Overflow condition
0 RX input shifter stops all activity on receiver Overflow condition

Bit 6 – RXPOL: Receive Polarity Control

Receive Polarity Control

ValueDescription
1 Invert RX polarity, Idle state is low
0 RX polarity is not inverted, Idle state is high

Bits 5:4 – STP[1:0]: Stop Bit Mode Control(1)

Stop Bit Mode Control(1)

ValueDescription
11 Transmit 2 Stop bits, receiver verifies first Stop bit
10 Transmit 2 Stop bits, receiver verifies first and second Stop bits
01 Transmit 1.5 Stop bits, receiver verifies first Stop bit
00 Transmit 1 Stop bit, receiver verifies first Stop bit

Bit 3 – C0EN: Checksum Mode Select(2)

Checksum Mode Select(2)

ValueNameDescription
1 MODE = LIN Enhanced LIN checksum includes PID in sum
0 MODE = LIN Legacy LIN checksum does not include PID in sum
1 MODE = not LIN Checksum is the sum of all TX and RX characters
0 MODE = not LIN Checksum is disabled

Bit 2 – TXPOL: Transmit Control Polarity(1)

Transmit Control Polarity(1)

ValueDescription
1 Output data is inverted, TX output is low in Idle state
0 Output data is not inverted, TX output is high in Idle state

Bits 1:0 – FLO[1:0]: Handshake Flow Control

Handshake Flow Control

ValueDescription
11 Reserved
10 RTS/CTS and TXDE Hardware flow control
01 XON/XOFF Software flow control
00 Flow control is off